ADT7476ARQH ONSEMI [ON Semiconductor], ADT7476ARQH Datasheet - Page 51

• Manufacturer Part Number: ADT7476ARQH
• Description: dBCOOL Remote Thermal Controller and Voltage Monitor
• Manufacturer: ONSEMI [ON Semiconductor]

1. These registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH
1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7476
1. These registers set the maximum PWM duty cycle of the PWM output.
2. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 19. Fan Tachometer Reading Registers (Power−On Default = 0x00)
Table 20. Current PWM Duty Cycle Registers (Power−On Default = 0xFF)
Table 21.PWM Maximum Duty Cycle (Power−On Default = 0xFF)
pulses (default = 2). The number of TACH pulses used to count can be changed using the TACH Pulses per Revolution register (Register 0x7B).
This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes be read, the low byte must
be read first. Both the low and high bytes are then frozen until read. At power−on, these registers contain 0x0000 until the first valid fan TACH
measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF
indicates that a fan is one of the following: stalled or blocked (object jamming the fan), failed (internal circuitry destroyed), or not populated. (The
ADT7476 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should
be set to 0xFFFF.) An alternate function, for example, is TACH4 reconfigured as the THERM pin.
reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed
control mode. During fan startup, these registers report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle
value by writing to these registers.
Register Address
Register Address
Register Address
0x2A
0x2B
0x2C
0x2D
0x2E
0x3A
0x28
0x29
0x2F
0x30
0x31
0x32
0x38
0x39
Read−only
Read−only
Read−only
Read−only
Read−only
Read−only
Read−only
Read−only
(Note 2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TACH1 low byte.
TACH1 high byte.
TACH2 low byte.
TACH2 high byte.
TACH3 low byte.
TACH3 high byte.
TACH4 low byte.
TACH4 high byte.
PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
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51
(Note 1 and 2)
Description
Description
Description
(Note 1)
(Note 1)