AT25DF641A-MH-T ATMEL [ATMEL Corporation], AT25DF641A-MH-T Datasheet - Page 44

• Manufacturer Part Number: AT25DF641A-MH-T
• Description: 64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

12.4
12.5
44
Resume from Deep Power-Down
Hold
Atmel AT25DF641A [Preliminary]
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume
from Deep Power-Down command must be issued. The Resume from Deep Power-Down com-
mand is the only command that the device will recognized while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of
ABh must be clocked into the device. Any additional data clocked into the device after the
opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Power-
Down mode within the maximum time of t
has returned to the standby mode, normal command operations such as Read Array can be
resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not
deasserted on an even byte boundary (multiples of eight bits), then the device will abort the
operation and return to the Deep Power-Down mode.
Figure 12-4. Resume from Deep Power-Down
The HOLD pin is used to pause the serial communication with the device without having to stop
or reset the clock sequence. The Hold mode, however, does not have an affect on any internally
self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in prog-
ress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until
it is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated
simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during
the SCK high pulse, then the Hold mode won’t be started until the beginning of the next SCK low
pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are
asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin
and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while
in the Hold mode.
SCK
SO
I
CS
CC
SI
Deep Power-Down Mode Current
HIGH-IMPEDANCE
MSB
1
0
Active Current
0
1
1
2
OPCODE
0
3
RDPD
1
4
0
5
and return to the standby mode. After the device
1
6
1
7
Standby Mode Current
t
RDPD
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