AT25DF641A-MH-T ATMEL [ATMEL Corporation], AT25DF641A-MH-T Datasheet - Page 9

• Manufacturer Part Number: AT25DF641A-MH-T
• Description: 64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

7. Read Commands
7.1
Figure 7-1.
8693A–DFLASH–8/10
SCK
SO
CS
SI
Read Array
HIGH-IMPEDANCE
MSB
Read Array - 1Bh Opcode
0
0
0
1
0
2
OPCODE
1
3
1
4
The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the clock signal once the initial starting address has been speci-
fied. The device incorporates an internal address counter that automatically increments on every
clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each
opcode depends on the maximum clock frequency that will be used to read data from the device.
The 0Bh opcode can be used at any clock frequency up to the maximum specified by f
the 03h opcode can be used for lower frequency read operations up to the maximum specified
by f
clock frequency up to the maximum specified by f
frequencies above f
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (1Bh, 0Bh, or 03h) must be clocked into the device. After the opcode has been clocked
in, the three address bytes must be clocked in to specify the starting address location of the first
byte to read within the memory array. Following the three address bytes, additional dummy
bytes may need to be clocked into the device depending on which opcode is used for the Read
Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must
be clocked in after the address bytes.
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have
been clocked in, additional clock cycles will result in data being output on the SO pin. The data is
always output with the MSB of a byte first. When the last byte (7FFFFFh) of the memory array
has been read, the device will continue reading back at the beginning of the array (000000h). No
delays will be incurred when wrapping around from the end of the array to the beginning of the
array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
0
5
1
6
RDLF
1
7
MSB
A
8
. The 1Bh opcode allows the highest read performance possible and can be used at any
A
9
ADDRESS BITS A23-A0
A
10 11
A
A
12
A
CLK
should be reserved to systems employing the Atmel
A
29 30
A
A
31 32
MSB
X
Atmel AT25DF641A [Preliminary]
X
33
DON'T CARE
X
34
X
35
X
36
X
37 38
X
X
39
MSB
X
40
MAX
X
41
DON'T CARE
X
; however, use of the 1Bh opcode at clock
42 43
X
X
44
X
45
X
46
X
47 48
MSB
D
D
49
DATA BYTE 1
D
50 51
D
®
D
52
RapidS protocol.
D
53
D
54
D
55 56
MSB
D
D
CLK
, and
9