M58LT256JSB8ZA6 STMICROELECTRONICS [STMicroelectronics], M58LT256JSB8ZA6 Datasheet
M58LT256JSB8ZA6
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M58LT256JSB8ZA6 Summary of contents
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... Programming time – 5 µs typical Word program time using Buffer Enhanced Factory Program command Memory organization – Multiple Bank memory array: 16 Mbit banks – Parameter Blocks (top or bottom location) Dual operations – program/erase in one Bank while read in others – No delay between read and write ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M58LT256JST, M58LT256JSB 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 6.9 Burst length bits (CR2-CR0 ...
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M58LT256JST, M58LT256JSB List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 48. Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 103 Table ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. TBGA64 package connections (top view through package Figure 3. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 5. X-Latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 6. Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 7. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 8. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 9 ...
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... Each block can be erased separately. Erase can be suspended, in order to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the ...
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... WAIT DDQ SSQ NC DU Figure 4, shows the Protection Register Memory map DDQ V PP A0-A23 W E M58LT256JST G M58LT256JSB SSQ Function Address inputs Data input/outputs, command inputs Chip Enable Output Enable Write Enable ...
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Description Figure 2. TBGA64 package connections (top view through package DQ8 F K A22 10/106 A12 ...
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... M58LT256JST, M58LT256JSB Table 2. Bank architecture Number Parameter Bank Bank 1 Bank 2 Bank 3 Bank 14 Bank 15 Figure 3. Memory map M58LT256JST - Top Boot Block 000000h 00FFFFh Bank 15 0F0000h 0FFFFFh C00000h C0FFFFh Bank 3 CF0000h CFFFFFh D00000h D0FFFFh Bank 2 DF0000h DFFFFFh E00000h E0FFFFh Bank 1 EF0000h EFFFFFh F00000h ...
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... Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 2.6 Reset (RP) The Reset input provides a hardware reset of the memory. When Reset memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply current I for the value of I DD2 ...
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... Reset one clock cycle in advance. 2.10 V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (Read, Program and Erase). 2.11 V supply voltage DDQ V provides the power supply to the I/O pins and enables all outputs to be powered ...
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Signal descriptions 2.13 V ground SS V ground is the reference for the core supply. It must be connected to the system ground. SS 2.14 V ground SSQ V ground is the reference for the input/output circuitry driven by V ...
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... Read ac characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at V Enable Commands, Input Data and Addresses are latched on the rising edge of IH Write Enable or Chip Enable, whichever occurs first ...
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... Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at V consumption is reduced to the standby level I independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V during a program or erase operation, the device enters Standby mode when finished. ...
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... M58LT256JST, M58LT256JSB 4 Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation ...
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... The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations will output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank ...
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... Parameter Bank and the CFI memory space are not allowed (see limitations for details). See Appendix B: Common Flash for details on the information contained in the Common Flash Interface memory area. for details). Interface, Tables 35, 36, 37, 38, 39, 40, 41, 42, Command interface Table 8). ...
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Command interface 4.5 Clear Status Register command The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1 and 5) in the Status Register. One Bus Write cycle is required to issue ...
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M58LT256JST, M58LT256JSB 4.7 The Blank Check command The Blank Check command is used to check whether a Main Array Block has been completely erased. Only one Block at a time can be checked. To use the Blank Check command V ...
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... Command interface 4.8 Program command The program command is used to program a single word to the memory array. If the block being programmed is protected, then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the Program command. ...
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... Clear the Status Register before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored ...
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Command interface 4.10 Buffer Enhanced Factory Program command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical used to program one or more Write ...
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... Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next word. 3. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. ...
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Command interface 4.11 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One ...
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... Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Dual operation limitations The two Protection Register Locks are used to protect the OTP segments from further modification ...
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Command interface 4.14 Set Configuration Register command The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command. The first cycle sets ...
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M58LT256JST, M58LT256JSB Table 5. Standard commands Commands Read Array Read Status Register Read Electronic Signature Read CFI query Clear Status Register Block Erase Program (4) Buffer Program Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Protect Block ...
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Command interface Table 6. Factory commands Command Phase Blank Check Setup Buffer Enhanced Program/ Factory Verify Program Exit Word Address in targeted bank, BKA = Bank Address, PD =Program Data Block Address Don’t ...
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... M58LT256JST, M58LT256JSB Figure 4. Protection Register memory map Protection Register Lock PROTECTION REGISTERS 109h PR16 User Programmable OTP 102h 91h PR1 User Programmable OTP 8Ah 89h 88h 88h PR0 User Programmable OTP 85h 84h Unique device number ...
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Command interface Table 8. Protection Register locks Lock Number Address Lock 1 80h Lock 2 89h 32/106 Bits pre-programmed to protect Unique Device Number, address Bit 0 81h to 84h in PR0 Bit 1 protects 64 bits of OTP segment, ...
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... The Erase Suspend Status bit indicates that an erase operation has been suspended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive) ...
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... PP , the memory is protected and program and erase operations cannot PPLK Status bit must be set Low by a Clear Status Register command or PP M58LT256JST, M58LT256JSB ...
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... The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new word to be programmed to the memory array. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to ‘ ...
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Status Register Table 9. Status Register bits Bit Name SR7 P/E.C. Status Erase Suspend SR6 Status Erase/Blank Check SR5 Status SR4 Program Status SR3 V Status PP Program Suspend SR2 Status Block Protection SR1 Status Bank Write Status SR0 Multiple ...
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... M58LT256JST, M58LT256JSB 6 Configuration Register The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read modes section for details on read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1) ...
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... WAIT state. 6.6 Burst Type bit (CR7) The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses only. See Table 12: Burst type starting address in sequential mode. ...
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M58LT256JST, M58LT256JSB 6.7 Valid Clock Edge bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) ...
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Configuration Register Table 11. Configuration Register Bit CR15 Read Select CR14 Reserved CR13-CR11 X-Latency CR10 Wait Polarity Data Output CR9 Configuration CR8 Wait Configuration CR7 Burst Type CR6 Valid Clock Edge CR5-CR4 Reserved CR3 Wrap Burst CR2-CR0 Burst Length 1. ...
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M58LT256JST, M58LT256JSB Table 12. Burst type definition Start Add. 4 words 0 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-0 1-2-3-4-5-6-7-0 2 2-3-0-1 2-3-4-5-6-7-0-1 3 3-0-1-2 3-4-5-6-7-0-1-2 ... 7 7-4-5-6 7-0-1-2-3-4-5-6 ... 12-13-14-15-8-9- 12 12-13-14-15 13-14-15-8-9-10- 13 13-14-15-12 14-15-8-9-10-11- 14 14-15-12-13 15-8-9-10-11-12- 15 15-12-13-14 ...
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Configuration Register Figure 5. X-Latency and data output configuration example 1st cycle A23-A0 VALID ADDRESS tDELAY tAVK_CPU DQ15-DQ0 1. The settings shown are X-latency = 4, Data Output held for one clock cycle. Figure 6. Wait configuration ...
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... Asynchronous Read mode In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations. ...
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... In Synchronous Burst Read mode the data is output in bursts synchronized with the clock possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used ...
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... Single Synchronous Read mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is asserted during the X-latency and at the end and 16 word burst ...
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... Dual operations and multiple bank architecture The multiple bank architecture of the M58LT256JST/B gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased ...
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M58LT256JST, M58LT256JSB Table 14. Dual operations allowed in same bank Status of bank Read Array Idle Programming Erasing Program Yes Suspended Erase Yes Suspended 1. The Read Array command is accepted but the data output is not guaranteed until the ...
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Block protection 9 Block protection The M58LT256JST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency. This protection scheme has two levels of protection. Protect/Unprotect - this first level allows ...
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M58LT256JST, M58LT256JSB 9.4 Protection operations during Erase Suspend Changes to block protection status can be performed during an erase suspend by using the standard protection command sequences to unprotect or protect a block. This is useful in the case when ...
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... Table 16. Exact Erase times may change depending on the memory array condition. The best case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is when all the bits in the block are at ‘1’ (not pre-programmed). Usually, the system overhead is negligible with respect to the Erase time ...
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M58LT256JST, M58LT256JSB 11 Maximum rating Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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DC and ac parameters 12 DC and ac parameters This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics tables that follow, are derived from tests ...
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M58LT256JST, M58LT256JSB Figure 8. AC measurement load circuit Table 19. Capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. V DDQ V DD DEVICE UNDER TEST 0.1µF 0.1µ includes JIG capacitance ...
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DC and ac parameters Table 20. DC characteristics - currents Symbol I Input Leakage current LI I Output Leakage current LO Supply current Asynchronous Read (f=5 MHz) I DD1 Supply current Synchronous Read (f=52 MHz) I Supply current (Reset) DD2 ...
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M58LT256JST, M58LT256JSB Table 21. DC characteristics - voltages Symbol Parameter V Input Low voltage IL V Input High voltage IH V Output Low voltage OL V Output High voltage Program voltage-logic PP1 Program voltage ...
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DC and ac parameters Figure 9. Asynchronous Random Access Read ac waveforms 56/106 M58LT256JST, M58LT256JSB ...
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M58LT256JST, M58LT256JSB Figure 10. Asynchronous Page Read ac waveforms DC and ac parameters 57/106 ...
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DC and ac parameters Table 22. Asynchronous Read ac characteristics Symbol Alt t t AVAV t t AVQV ACC t t AVQV1 PAGE ( AXQX t ELTV ( ELQV (1) t ELQX t EHTZ (1) t ...
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M58LT256JST, M58LT256JSB Figure 11. Synchronous Burst Read ac waveforms DC and ac parameters 59/106 ...
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DC and ac parameters Figure 12. Single Synchronous Read ac waveforms A0-A23 L ( Hi-Z DQ0-DQ15 Hi-Z (1,2) WAIT 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 2. ...
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M58LT256JST, M58LT256JSB Figure 13. Synchronous Burst Read Suspend ac waveforms DC and ac parameters 61/106 ...
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DC and ac parameters Figure 14. Clock input ac waveform Table 23. Synchronous Read ac characteristics Symbol t AVKH t ELKH t EHEL t EHTZ t KHAX t KHQV t KHTV t KHQX t KHTX t t LLKH ADVLCLKH t ...
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M58LT256JST, M58LT256JSB Figure 15. Write ac waveforms, Write Enable controlled DC and ac parameters 63/106 ...
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DC and ac parameters Table 24. Write ac characteristics, Write Enable controlled Symbol Alt t t AVAV WC t AVLH (3) t AVWH t t DVWH DS t ELLH t t ELWL CS t ELQV t ELKV t GHWL t ...
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M58LT256JST, M58LT256JSB Figure 16. Write ac waveforms, Chip Enable controlled DC and ac parameters 65/106 ...
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DC and ac parameters Table 25. Write ac characteristics, Chip Enable controlled Symbol t AVAV t AVEH t AVLH t DVEH t EHAX t EHDX t EHEL t EHGL t EHWH t ELKV t ELEH t ELLH t ELQV t ...
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M58LT256JST, M58LT256JSB Figure 17. Reset and Power-up ac waveforms tVDHPH VDD, VDDQ Table 26. Reset and Power-up ac characteristics Symbol Parameter Reset Low to t PLWL Write Enable Low, t PLEL Chip Enable Low, t ...
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Package mechanical 13 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box ...
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M58LT256JST, M58LT256JSB Table 27. TBGA64 10 × active ball array pitch, package mechanical data Symbol 10.000 D1 ddd e E 13.000 millimeters ...
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... T = Tape & Reel Packing Blank = Standard packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...
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M58LT256JST, M58LT256JSB Appendix A Block address tables The following set of equations can be used to calculate a complete set of block addresses using the information contained in Tables To calculate the Block Base Address from the Block Number: First ...
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Block address tables Table 29. M58LT256JST - parameter bank block addresses Block number 72/106 Size (kwords ...
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M58LT256JST, M58LT256JSB Table 30. M58LT256JST - main bank base addresses Bank number There are two bank regions: bank region 1 contains all the banks ...
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Block address tables Table 32. M58LT256JSB - parameter bank block addresses Block number 74/106 Size (kwords ...
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M58LT256JST, M58LT256JSB Table 33. M58LT256JSB - main bank base addresses Bank number There are two Bank Regions: Bank Region 2 contains all the banks ...
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... Alternate algorithm-specific extended A query table 080h Security code area 1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 36, 37, lowest order data outputs. 76/106 Sub-section name Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & ...
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M58LT256JST, M58LT256JSB Table 36. CFI query identification string Offset Sub-section name 000h 001h 002h-00Fh 010h 011h 012h 013h 014h 015h offset = P = 000Ah Address for primary algorithm extended query table 016h 017h 018h 019h value = A = ...
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Common Flash Interface Table 37. CFI query system interface information Offset Data 01Bh 0017h 01Ch 0020h 01Dh 0085h 01Eh 0095h 01Fh 0008h 020h 0009h 021h 000Ah 022h 0000h 023h 0001h 024h 0001h 025h 0002h 026h 0000h 78/106 Description V Logic ...
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M58LT256JST, M58LT256JSB Table 38. Device geometry definition Offset Data 027h 0019h 028h 0001h 029h 0000h 02Ah 0006h 02Bh 0000h 02Ch 0002h 02Dh 00FEh 02Eh 0000h 02Fh 0000h 030h 0002h 031h 0003h 032h 0000h 033h 0080h 034h 0000h 035h Reserved Reserved ...
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Common Flash Interface Table 39. Primary algorithm-specific extended query table Offset (P)h = 10Ah 0050h 0052h 0049h (P+3)h =10Dh 0031h Major version number, ASCII (P+4)h = 10Eh 0033h Minor version number, ASCII (P+5)h = 10Fh 00E6h Extended query table contents ...
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M58LT256JST, M58LT256JSB Table 40. Protection register information Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h ...
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Common Flash Interface Table 41. Burst Read information Offset (P+1D)h = 127h (P+1E)h = 128h (P+1F)h = 129h (P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch 82/106 Data Description Page-mode read capability n bits 0-7 n’ such that 2 ...
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M58LT256JST, M58LT256JSB Table 42. Bank and Erase block region information M58LT256JST Offset (P+23)h = 12Dh 1. The variable pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Tables Table ...
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Common Flash Interface Table 43. Bank and Erase block region 1 information (continued) M58LT256JST Offset Data (P+30)h = 13Ah 02h (P+31)h = 13Bh 03h 1. The variable pointer which is defined at CFI offset 015h. 2. Bank ...
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M58LT256JST, M58LT256JSB Table 44. Bank and Erase block region 2 information M58LT256JST Offset Data (P+32)h = 13Ch 01h (P+33)h = 13Dh 00h (P+34)h = 13Eh 11h (P+35)h = 13Fh 00h (P+36)h = 140h 00h (P+37)h = 141h 02h (P+38)h = ...
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Common Flash Interface Table 44. Bank and Erase block region 2 information (continued) M58LT256JST Offset Data (P+40)h = 14Ah 03h (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h (P+44)h = 14Eh 64h (P+45)h = 14Fh 00h ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 88/106 blank_check_command (blockToCheck) { writeToFlash (blockToCheck, 0xBC); writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */ (status_register.SR4==1) && (status_register.SR5==1) Command Sequence /* command sequence error */ Error (2) if (status_register ...
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... Routine for Error Check by reading SR3, SR4 and SR1. Buffer_Program_command (Start_Address, n, buffer_Program buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+ {writeToFlash (Start_Address, 0xE8) ; ...
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Flowcharts and pseudocodes Figure 22. Program Suspend & Resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR2 = 1 YES Write FFh Read data from another address Write D0h (1) ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used. erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; writeToFlash (blockToErase, 0xD0 Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase must be toggled*/ } while (status_register.SR7== 0) ...
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Flowcharts and pseudocodes Figure 24. Erase Suspend & Resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block or Program or ...
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M58LT256JST, M58LT256JSB Figure 25. Protect/Unprotect operation flowchart and pseudocode Start Write 60h (1) Write 01h, D0h Write 90h (1) Read Block Protect State Protection change confirmed? YES Write FFh (1) End 1. Any address within the bank can equally be ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 94/106 protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 ...
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M58LT256JST, M58LT256JSB Figure 27. Buffer Enhanced Factory Program flowchart and pseudocode Address WA1 Address WA1 Read Status NO NO Initialize count SR4 = 1 Read Status Register Address WA1 SR3 and SR1for errors Increment Count Exit Write ...
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Command interface state tables Appendix D Command interface state tables Table 45. Command Interface states - modify table, next state Current CI State Program Read Program (3)(4) (2) Setup Array (FFh) (10/40h) Program Ready Ready Setup Protect/CR Setup Ready (Protect ...
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M58LT256JST, M58LT256JSB Table 45. Command Interface states - modify table, next state Current CI State Program Read Program (3)(4) (2) Setup Array (FFh) (10/40h) Setup IS in Erase Busy Erase Busy Busy IS in Erase Erase Busy Erase Program Suspend ...
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Command interface state tables Table 45. Command Interface states - modify table, next state Current CI State Program Read Program (3)(4) (2) Setup Array (FFh) (10/40h) Setup Blank Check Busy Protect/CR Setup Erase Suspend (Protect Error) in Erase Suspend Setup ...
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M58LT256JST, M58LT256JSB Table 46. Command Interface states - modify table, next output state Read Program Current CI State (4) Array Setup Program (3) (5) (FFh) (10/40h) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP ...
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Command interface state tables Table 46. Command Interface states - modify table, next output state Read Program Current CI State (4) Array Setup Program (3) (5) (FFh) (10/40h) OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend ...
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M58LT256JST, M58LT256JSB Table 47. Command interface states - lock table, next state Current CI State Protect/CR Setup (60h) Ready Protect/CR Setup Protect/CR Setup Ready (Protect error) Setup OTP Busy IS in OTP Busy IS in OTP busy Setup Busy IS ...
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Command interface state tables Table 47. Command interface states - lock table, next state Current CI State Protect/CR Setup (60h) Setup Busy IS in Program busy in ES Program IS in Program in Erase busy in ES Suspend Suspend IS ...
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M58LT256JST, M58LT256JSB Table 48. Command interface states - lock table, next output state Current CI State Protect/CR Setup Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer ...
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Command interface state tables Table 48. Command interface states - lock table, next output state (continued) Current CI State Protect/CR Setup OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase ...
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... Figure 24: Erase Suspend & Resume flowchart and pseudocode modified. Appendix D: Command interface state tables Document status promoted from Target Specification to Preliminary Data. Small text changes. Output Enable modified. Section 6.9: Burst length bits (CR2-CR0) Device architecture corrected (see Figure 3: Memory map I and I parameter values updated in DD1 DD6 characteristics - currents. ...
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