HYB39S256160DC-6

Manufacturer Part NumberHYB39S256160DC-6
Description256 MBit Synchronous DRAM
ManufacturerINFINEON [Infineon Technologies AG]
HYB39S256160DC-6 datasheet
 
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256 MBit Synchronous DRAM
High Performance:
-6
-7
-7.5
fCK
166
143
133
tCK3
6
7
7.5
tAC3
5
5.4
5.4
tCK2
7.5
7.5
10
tAC2
5.4
5.4
6
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page
Multiple Burst Read with Single Write
Operation
Automatic
and
Controlled
Command
The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54
packages.
INFINEON Technologies
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
-8
Units
Auto Refresh (CBR) and Self Refresh
125
MHz
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
8
ns
Random Column Address every CLK
6
ns
( 1-N Rule)
10
ns
Single 3.3V +/- 0.3V Power Supply
6
ns
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
Chipsize Packages:
54 ball TFBGA (12 mm x 8 mm)
-6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
Precharge
1
2002-04-23