HYB39S256160DC-6 INFINEON [Infineon Technologies AG], HYB39S256160DC-6 Datasheet - Page 8

• Manufacturer Part Number: HYB39S256160DC-6
• Description: 256 MBit Synchronous DRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Signal Pin Description
Pin
CLK
CKE
CS
RAS
CAS
WE
A0 - A12
BA0, BA1 Input
DQx
INFINEON Technologies
Type
Input
Input
Input
Input
Input
Input
Output
Signal Polarity Function
Pulse
Level
Pulse
Pulse
Level
Level
Level
Positive
Edge
Active
High
Active
Low
Active
Low
–
–
–
The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiating either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
During a Bank Activate command cycle, A0-A12 define the
row address (RA0-RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-An define the
column address (CA0-CAn) when sampled at the rising
clock edge.CAn depends upon the SDRAM organization:
64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8 SDRAM
16M x16 SDRAM
In addition to the column address, A10(= AP) is used to
invoke the autoprecharge operation at the end of the burst
read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged.
If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
Bank Select Inputs. Bank address inputs selects which of
the four banks a command applies to.
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
8
HYB39S256400/800/160DT(L)/DC(L)
CAn = CA9
CAn = CA8
256MBit Synchronous DRAM
(Page Length = 1024 bits)
(Page Length = 512 bits)
2002-04-23