HYB39S256160DC-6 INFINEON [Infineon Technologies AG], HYB39S256160DC-6 Datasheet

HYB39S256160DC-6

Manufacturer Part Number

HYB39S256160DC-6

Description

256 MBit Synchronous DRAM

Manufacturer

INFINEON [Infineon Technologies AG]

Datasheet

1.HYB39S256160DC-6.pdf (22 pages)

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256 MBit Synchronous DRAM

•

The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x

16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices

achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that

prefetches multiple bits and then synchronizes the output data to a system clock. The chip is

fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.

The device is designed to comply with all industry standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is

possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single

3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54

packages.

INFINEON Technologies

tCK3

tAC3

tCK2

tAC2

fCK

High Performance:

Fully Synchronous to Positive Clock Edge

0 to 70 °C operating temperature

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2 & 3

Programmable Wrap Sequence: Sequential

or Interleave

Programmable Burst Length:

1, 2, 4, 8 and full page

Multiple Burst Read with Single Write

Operation

Automatic

Command

166

7.5

5.4

-6

and

143

5.4

7.5

5.4

-7

Controlled

-7.5

133

7.5

5.4

125

-8

Precharge

Units

MHz

HYB39S256400/800/160DT(L)/DC(L)

•

Data Mask for Read / Write control (x4, x8)

Data Mask for byte control (x16)

Auto Refresh (CBR) and Self Refresh

Power Down and Clock Suspend Mode

8192 refresh cycles / 64 ms (7,8 µs)

Random Column Address every CLK

( 1-N Rule)

Single 3.3V +/- 0.3V Power Supply

LVTTL Interface versions

Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

Chipsize Packages:

54 ball TFBGA (12 mm x 8 mm)

-6 parts for PC166 3-3-3 operation

-7 parts for PC133 2-2-2 operation

-7.5 parts for PC133 3-3-3 operation

-8 parts for PC100 2-2-2 operation

256MBit Synchronous DRAM

2002-04-23

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