HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet
HYB18T512161B2F-20/25
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HYB18T512161B2F-20/25 Summary of contents
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... Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 2 Internet Data Sheet ...
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... Full Strength and reduced Strength (60%) Data-Output Drivers • 2kB page size • Packages: P-TFBGA-84 1) • RoHS Compliant Products Ordering Information for RoHS compliant products Org. Clock (MHz) ×16 500/400 3 Internet Data Sheet HYB18T512161B2F–20/25 T lower than 85 CASE TABLE 1 Package P-TFBGA-84 ...
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... Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling) ...
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... HIGH throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) SSTL SSTL SSTL Chip Select 5 Internet Data Sheet HYB18T512161B2F–20/25 Figure 1. TABLE 2 ...
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... SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Strobe Upper Byte Note: UDQS corresponds to the data on DQ[15:8] SSTL SSTL Data Strobe Lower Byte Note: LDQS corresponds to the data on DQ[7:0] SSTL 6 Internet Data Sheet HYB18T512161B2F–20/25 ...
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... Power Supply – Power Supply – Not Connected SSTL On-Die Termination Control Note: ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. An EMRS(1) control bit enables or disables the ODT functionality. 7 Internet Data Sheet HYB18T512161B2F–20/25 TABLE 3 Abbreviations for Ball Type ...
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... Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Abbreviations for Buffer Type Chip Configuration, PG-TFBGA-84 (top view) 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8] ...
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... Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred to as ’colbits’ 2) Referred to as ’org’ colbits × org/8 [Bytes 3) PageSize = 2 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 512-Mbit DDR2 Addressing 32-Mbit x 16 BA[1:0] 4 A10 / AP A[12:0] A[9: 2048 (2K) ...
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... TM Vendor specific test mode B CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 010 CL reserved B 011 100 101 110 111 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 512-Mbit Double-Data-Rate-Two SDRAM Mode Register Definition (BA[1:0] = 00B Internet Data Sheet HYB18T512161B2F–20/25 TABLE 6 ...
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... QOff Output buffers enabled QOff Output buffers disabled DQS Enable DQS Disable OCD OCD calibration mode exit, maintain setting OCD Drive (1) OCD Drive (0) OCD Adjust mode OCD OCD calibration default 11 Internet Data Sheet HYB18T512161B2F–20/25 (in ns (in ns) and CK.MIN TABLE 7 ...
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... RTT ∞ (ODT disabled) RTT 75 Ohm RTT 150 Ohm RTT 50 Ohm DIC Full (Driver Size = 100%) DIC Reduced DLL Enable DLL Disable A Address bits 2) 12 Internet Data Sheet HYB18T512161B2F–20/25 TABLE > 85°C CASE ...
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... A7 to "1" before the self t conditions are met and no Self Refresh command is issued REF EMRS(1) Address Bit A10 Internet Data Sheet HYB18T512161B2F–20/25 3) TABLE TABLE 10 ODT Truth Table EMRS(1) Address Bit A11 X X ...
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... Order of burst access for sequential addressing is “nibble- based” and therefore different from SDR or DDR components 14 Internet Data Sheet HYB18T512161B2F–20/25 EMRS(1) Address Bit A11 TABLE 11 Burst Length and Sequence Interleave Addressing (decimal ...
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... Internet Data Sheet HYB18T512161B2F–20/25 TABLE 12 Command Truth Table 1)2)3) A[12:11] A10 A[9:0] Note 4)5) OP Code 4) 4)6) 4) 4)5) Row Address 4)5)8) Column L Column ...
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... DESELECT or NOP L DESELECT or NOP L AUTOREFRESH H Refer to the Command Truth Table V )” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in REF (200 clocks) is satisfied. 16 Internet Data Sheet HYB18T512161B2F–20/25 TABLE 13 2) 4)5) Action (N) Note 7)8)11) Maintain Power-Down 7)9)10)11) Power-Down Exit 8)11)12) Maintain Self Refresh 9)12)13)14) ...
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... High Temperature Self Refresh has to be enabled by setting CASE Rating min V –1 –0 –0 –0.5 SS 125 –55 150 17 Internet Data Sheet HYB18T512161B2F–20/25 TABLE 15 Unit Notes 1)2)3)4) °C = 3.9 μ approximately 50% DD6 TABLE 16 Absolute Maximum Ratings Unit Notes max ...
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... Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage TT 1) HYB18T512161B2F–20/ tracks with tracks with V DDQ DD DDDL V 3) The value of may be selected by the user to provide optimum noise margin in the system. Typically the value of REF be about 0.5 × ...
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... IL(ac).MAX 3) AC timings are referenced with input waveforms switching from transitions. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test ...
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... The minimum value is equal the transmitting device and is expected to track variations in DDQ IX(ac the transmitting device and DDQ OX(ac) Differential DC and AC Input and Output Logic Levels Diagram 20 Internet Data Sheet HYB18T512161B2F–20/25 FIGURE 2 TABLE 22 Unit Notes 1) + 0.3 — DDQ 2) + 0.6 — DDQ 3) + 0.6 V DDQ ...
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... Low (18.75 ohms) Ohms) 10.7 11.5 16.0 16.6 21.0 21 CASE 1.8 V, typical process CASE DDQ CASE 21 Internet Data Sheet HYB18T512161B2F–20/25 TABLE 23 Nominal Nominal 2) 4) High (17.25 Maximum (15 Ohms) Ohms) –11.8 –13.3 –17.4 –20.0 –23.0 –27 1.7 V, any process DDQ 1.8 V, any process CASE DDQ = 1.9 V, any process ...
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... Input capacitance, all other input-only pins CDI Input capacitance delta, all other input-only pins CIO Input/output capacitance, DQ, DM, DQS, DQS CDIO Input/output capacitance delta, DQ, DM, DQS, DQS Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Input / Output Capacitance Min. Max. 1.0 2.0 — 0.25 1.0 1.75 — ...
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... Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DD V Maximum undershoot area below SS Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 512-Mbit Double-Data-Rate-Two SDRAM –20 0.5 0.5 0.80 0.80 AC Overshoot / Undershoot Diagram for Address and Control Pins 23 Internet Data Sheet HYB18T512161B2F–20/25 TABLE 26 –25 Unit 0.5 V 0.5 V 0.80 V.ns 0.80 V.ns FIGURE 4 ...
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... Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DDQ V Maximum undershoot area below SSQ AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM –20 –25 0.9 0.9 0.9 0.9 0.23 0.23 0.23 ...
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... RCD t 15 — stabilizes. During the period before REF REF V . See Chapter 7.1 for the reference load for timing measurements Internet Data Sheet HYB18T512161B2F–20/25 TABLE 28 Speed Grade Definition –25 Unit Note Min. Max. 1)2)3) 1)2)3)4) 3. 1)2)3) 1)2)3)4) 2 ...
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... IPW t 400 450 × × LZ(DQ) AC.MAX t t AC.MIN AC.MIN LZ(DQS) AC.MIN AC.MAX AC.MIN t 2 — 2 MRD 26 Internet Data Sheet HYB18T512161B2F–20/25 TABLE 29 1) Unit Notes 2)3)4)5)6) Max. +500 ps t — 0. — 0.55 CK 7)18 — – ...
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... During the period before REF REF V . See Chapter 5 for the reference load for timing measurements refers to the application clock period. WR refers and ). Internet Data Sheet HYB18T512161B2F–20/25 –25 Unit Notes 2)3)4)5)6) Min. Max – — HP QHS — 380 ps μs 13)14) — ...
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... In “low active power-down mode” (MR, A12 =”1”) a slow XARD Values Min AC.MIN AC.MIN 2.5 t AC.MIN AC.MIN AOND 28 Internet Data Sheet HYB18T512161B2F–20/ [cycles] = (ns)/ (ns) rounded MIN TABLE 30 Unit Note Max 0 ...
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... CKE is HIGH HIGH between valid RP RP(IDD) (IDD mA. OUT (IDD interval, CKE is HIGH HIGH between valid RFC(IDD) = 7.8 μs interval, CKE is LOW and CS is HIGH between REFI 29 Internet Data Sheet HYB18T512161B2F–20/25 TABLE 31 I Measurement Conditions DD Symbol Note I 1)2)3)4)5)6) DD0 I 1)2)3)4)5)6) DD1 , 1)2)3)4)5)6) I ...
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... DQ signals not including mask or strobes Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 512-Mbit Double-Data-Rate-Two SDRAM (IDD) RCD(IDD) I current measurements are defined in chapter 7 REF DDQ 30 Internet Data Sheet HYB18T512161B2F–20/25 Symbol Note 1)2)3)4)5)6) I DD6 I 1)2)3)4)5)6)7) DD7 -1 × CK(IDD) CK TABLE 32 Definition for I DD ...
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... Internet Data Sheet HYB18T512161B2F–20/25 TABLE 33 I Specification DD Unit Note ...
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... Package 7.1 Package Dimension Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Package Outline P-TFBGA-84 (top view) 32 Internet Data Sheet FIGURE 6 ...
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... Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the Industrial standard JESD-51 standard. 2) Junction to Case thermal resistance. The value has been obtained by simulation. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 512-Mbit Double-Data-Rate-Two SDRAM Package thermal characteristics 1) Theta_jA 2s0p 3 m/s 0 m Internet Data Sheet HYB18T512161B2F–20/25 TABLE 34 2) Theta_jC 3 m ...
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... Overshoot and Undershoot Specification 23 5.7 AC Characteristics 25 5.7.1 Speed Grade Definitions 25 5.7.2 AC Timing Parameters 26 5.7.3 ODT AC Electrical Characteristics 28 6 Specifications and Conditions 29 7 Package 32 7.1 Package Dimension 32 7.2 Package Thermal Characteristics 33 Contents 34 List of Tables 35 List of Figures 36 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 34 Internet Data Sheet ...
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... DD I Table 33 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DD Table 34 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM ) . . . . . . . . . . . . . . . . . . . . . . . . . . . Internet Data Sheet ...
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... Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4 AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6 Package Outline P-TFBGA-84 (top view Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 36 Internet Data Sheet ...
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Edition 2007-06 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...