HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 30

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2)
3)
4) Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for
6) Timing parameter minimum and maximum values for
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Parameter
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
Operating Bank Interleave Read Current
1. All banks interleaving reads,
Parameter
LOW
HIGH
STABLE
FLOATING
SWITCHING
V
I
I
t
bus inputs are stable during deselects; Data bus is switching.
DD
DD
CK(IDD)
DDQ
specifications are tested after the device is properly initialized.
parameter are specified with ODT disabled.
= 1.8 V ± 0.1 V;
,
t
RC
=
I
t
DD
RC(IDD)
Description
defined as
defined as
defined as inputs are stable at a HIGH or LOW level
defined as inputs are
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
: see
V
,
Table 32
DD
t
RRD
= 1.8 V ± 0.1 V
=
V
V
t
IN
IN
RRD(IDD)
I
≤
≥
OUT
V
V
IL(ac).MAX
IH(ac).MIN
= 0 mA; BL = 4, CL = CL
; CKE is HIGH, CS is HIGH between valid commands. Address
V
REF
=
V
DDQ
I
DD
/ 2
current measurements are defined in chapter 7..
30
(IDD)
, AL =
t
RCD(IDD)
512-Mbit Double-Data-Rate-Two SDRAM
-1 ×
t
CK(IDD)
;
t
CK
HYB18T512161B2F–20/25
=
Symbol
I
I
Internet Data Sheet
DD6
DD7
Definition for I
TABLE 32
Note
1)2)3)4)5)6)
1)2)3)4)5)6)7)
DD