HYB18T512800BF QIMONDA [Qimonda AG], HYB18T512800BF Datasheet - Page 20

• Manufacturer Part Number: HYB18T512800BF
• Description: 240-Pin Registered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
18) Input waveform timing
19) If
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
21)
22)
23) Input waveform timing is referenced from the input signal crossing at the
24) Input waveform timing is referenced from the input signal crossing at the
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
26)
27)
28)
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support
32)
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
The spec values are not affected by the amount of clock jitter applied (i.e.
crossing. That is, these parameters should be met whether clock jitter is present or not.
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
Figure
((L/U/R)DQS / DQS) crossing.
t
It is used in conjunction with t
following equation;
minimum of the actual instantaneous clock low time.
t
which specifies when the device output is no longer driving (
to the device under test. See
to the device under test. See
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
t
the max column. {The less half-pulse width distortion present, the larger the
Examples: 1) If the system provides
provides
t
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
t
(
driving (
calculation is consistent.
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
t
HP
HZ
QH
QHS
RPST
t
nRP
WTR
RPST
t
t
t
DS
JIT.PER.MAX
JIT.DUTY.MAX
is the minimum of the absolute half period of the actual input clock.
and
=
t
t
= RU{
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
is at lease two clocks (2 x
JIT.PER.MAX
JIT.DUTY.MAX
or
end point and
), or begins driving (
t
HP
3.
t
t
t
LZ
DH
RPRE
–
t
HP
t
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
t
RP
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
QHS
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
= 1.1 x
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
/
= 0.6 x
, where:
= + 93 ps, then
t
CK.AVG
= + 93 ps, then
t
t
HP
t
RPRE
CK.AVG
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
CK.AVG
t
= MIN (
DS
t
HP
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
RPRE
is the minimum of the absolute half period of the actual input clock; and
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
QHS
Figure
Figure
t
t
).
RPRE.MIN(DERATED)
CH.ABS
t
t
RPST.MIN(DERATED)
CK
Figure 2
to derive the DRAM output timing
) independent of operation frequency.
t
HP
,
4.
4.
t
CL.ABS
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
shows a method to calculate these points when the device is no longer driving (
), where,
=
=
t
RPRE.MIN
t
RPST.MIN
t
CH.ABS
+
+
t
t
JIT.PER.MIN
t
is the minimum of the actual instantaneous clock high time;
HZ
JIT.DUTY.MIN
), or begins driving (
20
t
QH
= 0.9 x
. The value to be used for
t
HP
= 0.4 x
t
V
V
QH
IL.DC
IH.AC
t
is an input parameter but not an input specification parameter.
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
JIT.PER
of 1080 ps minimum.
t
QH
t
CK.AVG
level for a rising signal and
level for a rising signal and
t
CK.AVG
value is; and the larger the valid data eye will be.}
,
t
JIT.CC
t
LZ
– 72 ps = + 2178 ps and
) .
– 72 ps = + 928 ps and
, etc.), as these are relative to the clock signal
t
nPARAM
240-Pin Registered DDR2 SDRAM
t
= RU{
V
t
QH
QH
IL.AC
t
QHS
t
t
calculation is determined by the
of 975 ps minimum. 2) If the system
JIT.PER
JIT.DUTY
t
t
nRP
RP
level to the differential data strobe
t
PARAM
is the specification value under
V
V
= 15 ns, the device will support
= RU{
IH.DC
IL.AC
of the input clock. (output
t
of the input clock. (output
t
V
RPRE.MAX(DERATED)
RPST.MAX(DERATED)
/
il(DC)MAX
for a falling signal applied
t
for a falling signal applied
CK.AVG
t
Internet Data Sheet
t
RP
HP
/
t
t
at the input is
JIT.DUTY.MIN
JIT.PER.MIN
t
CK.AVG
}, which is in clock
and
t
t
t
RPST
JIT.PER
CL.ABS
V
}, which is in
ih(DC)MIN
), or begins
V
=
=
= – 72 ps
IH.AC
,
= – 72 ps
is the
t
t
t
RPRE.MAX
RPST.MAX
JIT.CC
. See
level
,