HYB18T512800BF QIMONDA [Qimonda AG], HYB18T512800BF Datasheet - Page 3

• Manufacturer Part Number: HYB18T512800BF
• Description: 240-Pin Registered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules with parity bit product family and
describes its main characteristics.
1.1
• 240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2
• One rank 64M ×72, 128M ×72, and two ranks 128M ×72,
• Registered DIMM Parity bit for address and control bus
• 512 MB, 1 GB, and 2 GB module built with 512 Mbit DDR2
• Standard Double-Data-Rate-Two Synchronous DRAMs
• Programmable CAS Latencies (3, 4, 5, 6), Burst Length
• Auto Refresh (CBR) and Self Refresh
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
Product Type Speed Code
Speed Grade
Max. Clock Frequency
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
SDRAM memory modules.
256M ×72 module organization, and 512M ×8, 512M ×4
chip organization
SDRAMs in P-TFBGA-60 chipsize packages.
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
(4 & 8) and Burst Type
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Overview
Features
@CL6
@CL5
@CL4
@CL3
f
f
f
f
t
t
t
t
CK6
CK5
CK4
CK3
RCD
RP
RAS
RC
–2.5F
PC2–6400
5–5–5
400
400
266
200
12.5
12.5
45
57.5
–2.5
PC2–6400
6–6–6
400
333
266
200
15
15
45
60
3
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• All inputs and outputs SSTL_18 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
• Serial Presence Detect with E
• RDIMM Dimensions (nominal): 30 mm high, 133.35 mm
• Based on standard reference card layouts Raw Card “F”,
• All speed grades faster than DDR2–400 comply with
• RoHS compliant products
Termination (ODT)
wide
“G“, “H“, ”J” and “L“
DDR2–400 timing specifications.
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
–3
PC2–5300
4–4–4
—
333
333
200
12
12
45
57
240-Pin Registered DDR2 SDRAM
–3S
PC2–5300
5–5–5
—
333
266
200
15
15
45
60
1)
2
PROM
Performance Table
Internet Data Sheet
–3.7
PC2–4200
4–4–4
—
266
266
200
15
15
45
60
TABLE 1
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns