HCS374D/SAMPLE INTERSIL [Intersil Corporation], HCS374D/SAMPLE Datasheet

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HCS374D/SAMPLE

Manufacturer Part Number
HCS374D/SAMPLE
Description
Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
November 11, 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1995, 1999, 2004
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCS374MS is a Radiation Hardened non-inverting
octal D-type, positive edge triggered flip-flop with three-stateable
outputs. The HCS374MS utilizes advanced CMOS/SOS technol-
ogy. The eight flip-flops enter data into their registers on the
LOW-to-HIGH transition of the clock (CP). Data is also
transferred to the outputs during this transition. The output
enable (OE) controls the three-state outputs and is independent
of the register operation. When the output enable is high, the out-
puts are in the high impedance state.
The HCS374MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS374MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS374DMSR
HCS374KMSR
HCS374D/Sample
HCS374K/Sample
HCS374HMSR
Day (Typ)
- Bus Driver Outputs - 15 LSTTL Loads
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
PART NUMBER
®
10
RAD (Si)/s 20ns Pulse
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
Flip-Flop, Three-State, Positive Edge Triggered
C
2
/mg
-9
o
o
C
C
Errors/Bit-
1
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
SCREENING LEVEL
Pinouts
GND
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
HCS374MS
Radiation Hardened Octal D-Type
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
OE
Q0
Q1
Q2
Q3
MIL-STD-1835 CDFP4-F20
D0
D1
D2
D3
MIL-STD-1835 CDIP2-T20
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Spec Number
20
19
18
17
16
15
14
13
12
11
File Number
20
19
18
17
16
15
14
13
12
PACKAGE
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
518770
2470.3
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP

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HCS374D/SAMPLE Summary of contents

Page 1

... SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCS374DMSR HCS374KMSR HCS374D/Sample HCS374K/Sample HCS374HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1995, 1999, 2004 HCS374MS Radiation Hardened Octal D-Type ...

Page 2

Functional Diagram ( 13, 14, 17, 18) D COMMON CONTROLS =High Level (Steady State) L =Low Level (Steady State) X =Immaterial Z =High Impedance ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Clock to Q TPLH, VCC = 4.5V TPHL Enable to Output TPZL, VCC = 4.5V TPZH Disable to Output TPLZ VCC = 4.5V TPHZ VCC = 4.5V NOTES: 1. All voltages referenced ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate Group A testing in ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams tr tf INPUT LEVEL 90 10% 10% TW TPLH VS Qn FIGURE 1. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE WIDTH TTLH VOH 80% 20% OUTPUT VOL FIGURE 3. OUTPUT TRANSITION TIME AC Load ...

Page 9

Three-State Low Timing Diagrams VIH INPUT VS VIL TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VT 2.25 VW 0.90 GND 0 VIL 0 Three-State High Timing Diagrams VIH INPUT VS ...

Page 10

Die Characteristics DIE DIMENSIONS: 108 x 106 mils METALLIZATION: Type: AlSi ± 1k Å Å Metal Thickness: 11k GLASSIVATION: Type: SiO 2 ± 2.6k Å Å Thickness: 13k WORST CASE CURRENT DENSITY < 2 A/cm BOND ...

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