MC9S08GW64_11 FREESCALE [Freescale Semiconductor, Inc], MC9S08GW64_11 Datasheet - Page 12

• Manufacturer Part Number: MC9S08GW64_11
• Description: HC08 instruction set with added BGND instruction
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
The average chip-junction temperature (T
where:
For most applications, P
is:
Solving
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
12
T

P
P
P
JA
D
int
I/O
A
Equation 1
= Ambient temperature, C
= P
= Package thermal resistance, junction-to-ambient, C/W
= I
= Power dissipation on input and output pins — user determined
ESD Protection and Latch-Up Immunity
A
int
Body Model
DD
. Using this value of K, the values of P
Latch-up
Charge
Model
Human
Device
Model
P
A
 V
.
and
I/O
DD
I/O
Equation 2
, Watts — chip internal power
 P
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
int
and can be neglected. An approximate relationship between P
for K gives:
Table 6. ESD and Latch-up Test Conditions
Description
K = P
MC9S08GW64 Series MCU Data Sheet, Rev. 3
J
) in C can be obtained from:
D
P
T
 (T
D
J
= K  (T
= T
A
D
+ 273C) + 
and T
A
+ (P
J
J
+ 273C)
can be obtained by solving
D
 
Symbol
JA
R1
R1
JA
—
—
C
C
)
 (P
D
)
2
Value
1500
–2.5
100
200
7.5
Equation 1
3
0
3
D
and T
and
Freescale Semiconductor
J
Equation 2
(if P
Unit
pF
pF


V
V
D
I/O
(at equilibrium)
is neglected)
iteratively
Eqn. 1
Eqn. 2
Eqn. 3