CA3130AT INTERSIL [Intersil Corporation], CA3130AT Datasheet - Page 5

• Manufacturer Part Number: CA3130AT
• Description: 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output
• Manufacturer: INTERSIL [Intersil Corporation]

through D
transients, including static electricity during handling for Q
and Q
NOTES:
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q
and its cascade-connected load resistance provided by
PMOS transistors Q
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
and zener diode Z
the series-connected circuit, consisting of resistor R
D
of resistor R
about 4.5V for PMOS transistors Q
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
7 to provide gate bias for PMOS transistors Q
should be noted that Q
both Q
be identical, the approximately 200 A current in Q
establishes a similar current in Q
sources for both the first and second amplifier stages,
respectively.
INPUT
6. Total supply voltage (for indicated voltage gains) = 15V with input
7. Total supply voltage (for indicated voltage gains) = 15V with out-
1
+
3
2
-
through D
terminals biased so that Terminal 6 potential is +7.5V above Ter-
minal 4.
put terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
7
2
CA3130
.
OFFSET
and Q
NULL
5
A
8
V
provide gate-oxide protection against high-voltage
1
1
4
5X
and diode D
, and PMOS transistor Q
3
. Since transistors Q
200 A
(WHEN REQUIRED)
1
BIAS CKT.
COMPENSATION
serve to establish a voltage of 8.3V across
3
and Q
1
1.35mA
is “mirror-connected (see Note 8)” to
4
6000X
C
A
provides a gate-bias potential of
5
V
C
. The source of bias potentials
5
2
200 A
and Q
4
1
1
8
and Q
, Q
with respect to Terminal
1
2
. A tap at the junction
3
A
, Q
30X
as constant current
V
5
STROBE
8mA
(NOTE 5)
0mA
(NOTE 7)
3
with respect to
2
are designed to
and Q
1
1
, diodes
CA3130, CA3130A
3
OUTPUT
. It
V+
V-
7
6
4
11
2
6
At total supply voltages somewhat less than 8.3V, zener
diode Z
developed across series-connected R
varies directly with variations in supply voltage.
Consequently, the gate bias for Q
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
NOTE:
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T
8. For general information on the characteristics of CMOS transis-
A
FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
= 25
tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.
17.5
12.5
7.5
2.5
15
10
5
0
o
1
C when Terminals 2 and 3 are at a common-mode
0
becomes nonconductive and the potential,
SUPPLY VOLTAGE: V+ = 15, V- = 0V
T
500
A
1k
CMOS OUTPUT STAGE
= 25
2.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
o
2k
C
LOAD RESISTANCE = 5k
5
7.5
10
4
, Q
12.5
5
1
, D
and Q
15
1
-D
4
2
17.5
, and Q
, Q
A
3
= 25
varies in
20
1
o
,
C.
22.5