AK4392 AKM [Asahi Kasei Microsystems], AK4392 Datasheet
AK4392
Related parts for AK4392
AK4392 Summary of contents
Page 1
... Digital Filter for better sound quality achieving low distortion characteristics and wide dynamic range. The AK4392 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4392 accepts 192kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including Blu-Ray, DVD-Audio and SACD ...
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... CCLK/DEM0 CDTI/DEM1 CAD0 CAD1/DIF0 PSN MS1045-E-02 VSS3 PDN 8X Interpolator DATT Soft Mute Control Clock Register Divider MCLK DZFL/DIF1 DIF2 Block Diagram - 2 - [AK4392] AVDD VSS4 VSS2 VDDL AOUTLP SCF AOUTLN VCML VREFHL ΔΣ Bias VREFLL Vref Modulator VREFLR VREFLL VCMR AOUTRP ...
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... Ordering Guide AK4392EQ AKD4392 ■ Pin Layout AOU TL P VCML VSS3 AVDD MCL K VSS4 NC MS1045-E-02 −10 ∼ +70°C 44pin LQFP (0.8mm pitch) Evaluation Board for AK4392 AK4392 Top View [AK4392] 22 AOUTRP 21 VCMR 20 NC ...
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... MS1045-E-02 PIN/FUNCTION Digital Power Supply Pin, 4.75 ∼ 5.25V Power-Down Mode Pin When at “L”, the AK4392 is in power-down mode and is held in reset. The AK4392 should always be reset upon power-up. Audio Serial Data Clock Pin in PCM Mode DSD Clock Pin in DSD Mode ...
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... Connect to GND. No internal bonding. Connect to GND. No internal bonding. Connect to GND. Ground Pin Analog Power Supply Pin, 4.75 ∼ 5.25V Master Clock Input Pin Ground Pin No internal bonding. Connect to GND [AK4392] (Internal pull-up pin) (Internal pull-down pin) (Internal pull-down pin) (Internal pull-down pin) 2009/04 ...
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... This pin must be open. TST2 This pin must be connected to VSS4. Setting These pins must be open. These pins must be open. These pins must be connected to VSS4. These pins must be open. Setting These pins must be open. These pins must be open. These pins must be open [AK4392] 2009/04 ...
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... AKM assumes no responsibility for the usage beyond the conditions in this data sheet. MS1045-E-02 ABSOLUTE MAXIMUM RATINGS Symbol AVDD VDDL/R DVDD IIN VIND Ta Tstg Symbol min AVDD 4.75 VDDL/R 4.75 DVDD 4.75 VREFHL/R AVDD−0.5 VREFLL/R VSS ΔVREF 3 [AK4392] min max −0.3 6.0 −0.3 6.0 −0.3 6.0 ±10 - −0.3 DVDD+0.3 −10 70 −65 150 typ max 5.0 5.25 5.0 5.25 5.0 5.25 - ...
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... The load resistance value is with respect to ground. Analog - 8 - [AK4392] typ max Units - 24 Bits -103 100 - dB - 100 - 120 dB 120 dB 120 dB ...
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... PR SA 100 13 Symbol min 12 Symbol min 12) SB 105 13 [AK4392] typ max Units 20.0 kHz 22.05 - kHz kHz ±0.005 1/fs ±0 typ max Units 43.5 kHz 48.0 - kHz kHz ±0.005 1/fs ±0 typ max Units 87 ...
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... PR SA 100 13 Symbol min 12 Symbol min 12) SB 105 13 [AK4392] typ max Units 20.0 kHz 22.05 - kHz kHz ±0.005 1/fs ±0 typ max Units 43.5 kHz 48.0 - kHz kHz ±0.005 1/fs ±0 typ max Units 87 ...
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... Note 14. The TST1/CAD0 and PSN pins have internal pull-up devices, nominally 100kΩ. Therefore The TST1/CAD0 and PSN pins are not included. MS1045-E-02 DC CHARACTERISTICS Symbol VIH VIL VOH DVDD−0.5 (Iout=100μA) VOL (Note 14) Iin - 11 - min typ max 2 0 0.5 ± [AK4392] Units μA 2009/04 ...
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... Units 41.472 MHz kHz 108 kHz 216 kHz ...
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... Note 15. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4392 should be reset by the PDN pin or RSTN bit. Note 16. BICK rising edge must not occur at the same time as LRCK edge. Note 17. DSD data transmitting device must meet this time. ...
Page 14
... Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”) MS1045-E-02 tLRB tSDS tSDH Audio Interface Timing (PCM Mode) tDCK tDCKL tDCKH tDDD tDCK tDCKL tDCKH tDDD tDDD - 14 - [AK4392] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2009/04 ...
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... CSN tCSS CCLK CDTI CSN CCLK CDTI D3 MS1045-E-02 tCCKL tCCKH tCDS tCDH C1 C0 R/W WRITE Command Input Timing D2 D1 WRITE Data Input Timing - 15 - [AK4392] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH D0 VIL 2009/04 ...
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... PDN WCK tBW BCK DATA MS1045-E-02 tPD Power Down & Reset Timing tWB tDS tDH External Digital Filter I/F mode - 16 - [AK4392] VIL VIH VIL VIH VIL VIH VIL 2009/04 ...
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... PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4392 should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4392 performs for only PCM data. ...
Page 18
... DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit. The AK4392 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”), and the analog output becomes Hi-Z. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4392 is in power-down mode until MCLK is supplied ...
Page 19
... Don’t care 19 0 Don’t care Figure 2. Mode 1/4 Timing - 19 - [AK4392] Table 7. In all formats the serial data BICK Figure ≥ 32fs Figure 1 ≥ 48fs Figure 2 ≥ 48fs Figure 3 (default) ≥ 48fs Figure 4 ≥ 48fs Figure 2 ≥ ...
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... Figure 5. Mode 5 Timing - Don’t care 1 Rch Data Don’t care Rch Data Rch Data [AK4392 2009/04 ...
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... Figure 8. DSD Mode Timing - Rch Data Rch Data [AK4392 2009/04 ...
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... The AK4392 is automatically placed in reset state when MCLK and WCK are stopped during a normal operation (PDN pin =“H”), and the analog output becomes Hi-Z. When MCLK and WCK are input again, the AK4392 exit reset state and starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4392 is in power-down mode until MCLK and WCK are supplied ...
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... Don’t care Don’t care Figure I/F Mode Timing - Don’t care Don’t care 3 0 [AK4392] 2009/04 ...
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... Output Volume The AK4392 includes channel independent digital output volumes (ATT) with 255 levels at linear step including MUTE. These volume control is in front of the DAC and it can attenuate the input data from 0dB to –127dB and mute. When changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions. ...
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... The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels are always “L”. The DZFB bit can invert the polarity of the DZF pin. ■ Mono Output The AK4392 can select input/output for both output channels by setting the MONO bit and SELLR bit. This function is available for any audio format. MONO bit 0 ...
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... System Reset The AK4392 should be reset once by bringing the PDN pin = “L” upon power-up. It initializes register settings of the device. The AK4392 exits this system reset (power-down mode) by MCLK and LRCK after the PDN pin = “H”, and the analog block exits power-down mode. The digital block exits power-down mode after the internal counter counts MCLK for 4/fs ...
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... Power ON/OFF timing The AK4392 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. the analog outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be muted externally if the click noise influences system application. ...
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... Reset Function (1) RESET by RSTN bit = “0” When the RSTN bit = “0”, the AK4392’s digital block is powered down, but the internal register values are not initialized. In this time, the analog outputs go to VCML/R voltage and DZFL/DZFR pins are “H”. ...
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... When MCLK and LRCK are input again, the AK4392 exits reset state and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4392 is in reset state when MCLK is stopped, and reset state when MCLK and WCK are stopped in external digital filter mode ...
Page 30
... When the state of the PSN pin is changed, the AK4392 should be reset by the PDN pin. The serial control interface is enabled by the PSN pin = “L”. In this mode, pin settings must be all “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit ...
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... MSB justified 00H Disable 01H Separated 01H Sharp roll-off filter 01H OFF 01H Normal Operation 01H PCM mode 02H 512fs 02H Stereo 02H “H” active 02H R channel 02H - 31 - [AK4392] Bit PCM DSD Ex DF I/F ATT7 EXDF Y - ESC - - DIF2 DZFE Y Y DZFM Y Y ...
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... When the PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default values. When the state of the PSN pin is changed, the AK4392 should be reset by the PDN pin. ■ Register Definitions ...
Page 33
... Disable (default) 1: Enable Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”. MS1045-E- DZFE DZFM (Table 10 DEM1 DEM0 [AK4392] D0 SMUTE 0 2009/04 ...
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... DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0: 512fs (default) 1: 768fs DP: DSD/PCM Mode Select 0: PCM Mode (default) 1: DSD Mode When D/P bit is changed, the AK4392 should be reset by RSTN bit. Addr Register Name 03H Lch ATT 04H Rch ATT Default ATT7-0: Attenuation Level 256 levels, 0.5dB step ...
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... Analog5. Lch Lch LPF Mute AOUTLN 33 VSS2 32 0 .1u 10u VDDL VREFHL 30 0.1u 10u VREFLL VREFLR 27 0 .1u 10u VR EFHR VDDR 25 0 .1u 10u VSS1 24 AOUTRN 23 Rch Rch LPF Mute + 10u + Electrolytic Capacitor Ceramic Capacitor [AK4392] Lch Out Rch Out 2009/04 ...
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... No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4392. 3. Analog Outputs The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R − ...
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... Stage 182kHz 0.637 +3.9dB 20kHz -0.025 40kHz -0.106 80kHz -0.517 - 37 - 1.5k 1n +Vop Analog Out -Vop 1n Gain +15 -15 0.1u 560 1.0n 620 620 1.0n NJM5534D + 10u 0. Stage Total 284kHz - - - -0.88dB +3.02dB -0.021 -0.046dB -0.085 -0.191dB -0.331 -0.848dB [AK4392] 10u + 100 Lch 2009/04 ...
Page 38
... It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4392 can achieve this filter response by combination of the internal filter AOUT- 2.8Vpp AOUT+ 2 ...
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... Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS1045-E-02 PACKAGE 0.20 S 0.6±0.15 S Epoxy, Halogen (bromine and chlorine) free Cu Solder (Pb free) plate - 39 - [AK4392] 1.60max 0.10±0.05 1.40 ±0.05 0.145±0.055 2009/04 ...
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... MS1045-E-02 MARKING AK4392EQ XXXXXXX AKM 1 1) Pin #1 indication 2) AKM Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK4392 5) Audio 4 pro Logo REVISION HISTORY Reason Page Contents First Edition Error Correct 37 Figure 19 was changed. Table 14 was changed. Description Short Delay Filter → Minimum Delay Filter ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1045-E-02 IMPORTANT NOTICE , and AKM assumes no responsibility for such use, except for the use Note2 [AK4392] in any safety, life support, or Note1) 2009/04 ...