AK4392 AKM [Asahi Kasei Microsystems], AK4392 Datasheet - Page 27

• Manufacturer Part Number: AK4392
• Description: High Performance 120dB Premium 32-Bit DAC
• Manufacturer: AKM [Asahi Kasei Microsystems]

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The AK4392 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. the analog
outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be
muted externally if the click noise influences system application.
The DAC can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding
analog outputs go to VCML/R. As some click noise occurs at the edge of RSTN signal, the analog output should be muted
externally if click noise aversely affect system performance.
Notes:
MS1045-E-02
Internal
State
Clock In
MCLK,LRCK,BICK
DZFL/DZFR
DAC In
DAC Out
External
Power
PDN pin
(Digital)
(Analog)
Mute
Power ON/OFF timing
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (3) adversely affect system performance
(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”).
The timing example is shown in this figure.
Don’t care
(1)
(3)
(6)
(4)
Figure 13. Power-down/up Sequence Example
Mute ON
“0”data
Normal Operation
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GD
(2)
“0”data
GD
(4)
(7)
Don’t care
(5)
Reset
Mute ON
(3)
[AK4392]
2009/04