XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 153

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

10.3 Core Timer Status and Control Register
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Address:
The read/write core timer status and control register (CTSCR) contains
the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and
the rate selects for the real-time interrupt as shown in
CTOF — Core Timer Overflow Flag
RTIF — Real-Time Interrupt Flag
Reset:
Read:
Write:
Figure 10-2. Core Timer Status and Control Register (CTSCR)
This read-only flag becomes set when the first eight stages of the core
timer counter roll over from $FF to $00. The CTOF flag bit generates
a timer overflow interrupt request if CTOFE is also set. The CTOF flag
bit is cleared by writing a logic 1 to the CTOFR bit. Writing to CTOF
has no effect. Reset clears CTOF.
This read-only flag becomes set when the selected real-time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. The RTIF enable bit is cleared by writing a
logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears
RTIF.
1 = Overflow in core timer has occurred.
0 = No overflow of core timer since CTOF last cleared
1 = Overflow in real-time counter has occurred.
0 = No overflow of real-time counter since RTIF last cleared
$0008
CTOF
Bit 7
0
= Unimplemented
RTIF
6
0
Core Timer
CTOFE
5
0
RTIE
4
0
Core Timer Status and Control Register
CTOFR
3
0
0
RTIFR
2
0
0
Figure
Advance Information
RT1
1
1
10-2.
Core Timer
Bit 0
RT0
1
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