XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 61

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

4.8 Programmable Timer Interrupts
4.8.1 Input Capture Interrupt
4.8.2 Output Compare Interrupt
4.8.3 Timer Overflow Interrupt
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
The 16-bit programmable timer can generate an interrupt whenever the
following events occur:
Setting the I bit in the condition code register disables timer interrupts.
The controls for these interrupts are in the timer control register (TCR)
located at $0012 and in the status bits in the timer status register (TSR)
located at $0013.
An input capture interrupt occurs if the input capture flag (ICF) becomes
set while the input capture interrupt enable bit (ICIE) is also set. The ICF
flag bit is in the TSR, and the ICIE enable bit is located in the TCR. The
ICF flag bit is cleared by a read of the TSR with the ICF flag bit set, and
then followed by a read of the LSB of the input capture register (ICRL)
or by reset. The ICIE enable bit is unaffected by reset.
An output compare interrupt occurs if the output compare flag (OCF)
becomes set while the output compare interrupt enable bit (OCIE) is also
set. The OCF flag bit is in the TSR and the OCIE enable bit is in the TCR.
The OCF flag bit is cleared by a read of the TSR with the OCF flag bit
set, and then followed by an access to the LSB of the output compare
register (OCRL) or by reset. The OCIE enable bit is unaffected by reset.
A timer overflow interrupt occurs if the timer overflow flag (TOF)
becomes set while the timer overflow interrupt enable bit (TOIE) is also
set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR.
•
•
•
Input capture
Output compare
Timer counter overflow
Interrupts
Programmable Timer Interrupts
Advance Information
Interrupts
61