MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 120

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.2.2
Address: 000A (Hex)
Label: MIER
Reset Value: 0000 (Hex)
Note: An interrupt will be generated on the IRQ pin if any of the above Interrupt Enable bits is set and there is a corresponding module-level
Service Request asserted in the Main Status Register at 0002h.
Address: 000C (Hex)
Label: MRR
Reset Value: 0001 (Hex)
Address: 1000 + p*2 (Hex)
Label: TXPTB_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
DATA_RXSAR_IE
RX_TIMEOUT_IE
SDT_RXSAR_IE
UDT_RXSAR_IE
TX_SAR_IE
UTOPIA_IE
XMEMA_IE
Reserved
TDM_IE
CPU_IE
TXCFG
TXPTB
Label
Label
Label
REV
TX_SAR Module
Position
Position
Position
15:14
15:9
15:0
13:0
Table 33 - TX_SAR Pointer Table Base Register (one per port)
Bit
Bit
Bit
0
1
2
3
4
5
6
7
8
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/O
Table 31 - Main Interrupt Enable Register
Table 32 - MT90520 Revision Register
TX_SAR Interrupt Enable.
SDT RX_SAR Interrupt Enable.
UDT RX_SAR Interrupt Enable.
TDM Interrupt Enable.
UTOPIA Interrupt Enable.
External Memory Arbiter Interrupt Enable.
Data RX_SAR Interrupt Enable.
Reassembly-Side Timeout Interrupt Enable.
CPU Interrupt Enable.
Always reads “0000_000”.
MT90520 hardware revision.
In SDT mode, these bits hold the base word address of the port p SDT Segmentation
Pointer Table (see Figure 21 on page 59). In UDT mode, these bits form a pointer to the
base word address of the UDT Segmentation Control Structure associated with port p.
The SDT Segmentation Pointer Tables must start on 32-word (64-byte) boundaries.
Port p Configuration:
“00” = Port p is disabled
“01” = UDT mode
“10” = Reserved
“11” = SDT mode.
Zarlink Semiconductor Inc.
MT90520
120
Description
Description
Description
Data Sheet