MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 71

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.6.1.3
In both the UDT and SDT modes of operation, each AAL1 cell which is destined for the RX_SAR has its AAL1
header byte processed by a sequence number checking process standardized in ITU-T I.363.1. The first portion of
the processing occurs in the Correction/Detection state machine, which is explained in this section. This algorithm
examines the received AAL1 byte and determines whether the sequence number protection on the byte is correct
by checking for CRC and parity errors. This state machine is primarily responsible for sending a corrected
sequence number and CSI bit to the Fast Sequence Number Processing state machine (outlined in Section 4.6.1.4)
for further sequence number processing.
Maximum Lead: Maximum allowable distance between the TDM Read Pointer and the SDT RX_SAR Write Pointer within a Reassembly Circular Buffer.
VC TDM Port: Identifies the TDM port (0 to 7) with which this VC is associated for slip detection and (optionally) for clock recovery.
First Entry: Indicates the location of the first Reassembly Circular Buffer Base Address within the Reassembly Control Structure. Must be programmed to
0Eh.
Last Entry: Indicates where the last Reassembly Circular Buffer Base Address is located within the Reassembly Control Structure. Must be programmed to
have the word-address of the last Reassembly Circular Buffer address (e.g., if n = 2, this field contains 0Fh).
A (Adaptive Enable): If set, the fill-level of the Reassembly Circular Buffer(s) associated with this VC are used to provide adaptive clocking information for the
VC TDM Port. Only one VC per TDM port can have this bit set.
S (SRTS Enable): If set, this VC is carrying RTS clocking information for the VC TDM Port. Only one VC per TDM port can have this bit set.
M (Multiframe Type): ‘0’ = DS1 (24 frames); ‘1’ = E1 (16 frames).
Structure Length: Indicates the length of the AAL1 structure, including TDM and CAS bytes. This field must be programmed by the user to be one less than
the actual structure length. For non-CAS VCs, this field is equal to the number of channels in the VC, less one. For CAS VCs, the formula for calculating the
Structure Length field is: DS1 = N*24 + roundup(N/2) - 1; E1 = N*16 + roundup(N/2) - 1.
CAS: If set, bit<0> indicates that this VC is carrying CAS information; if set, bit<1> indicates that the user wishes to control the CAS values via S/W (received
CAS values not written back to control structure); if set, bit<2> indicates that a CPU service request should be sent if the new CAS value for a channel differs
from the old (or if the received CAS value differs from the value set by hardware).
BS (Circular Buffer Size): “000” = 64 entries; “001” = 128 entries; “010” = 256 entries; “011” = 512 entries; “100” = 1024 entries; other = reserved.
Number of Channels: Indicates the number of channels within this VC. Field must be programmed by user to be one less than the actual number of channels
in the VC (possible values = 0d to 127d).
V_RTS<3:1> (RTS Validity): Bits indicating whether the individual bits in RTS<3:1> are valid and can therefore be used by the PLL for clock recovery
processing.
RTS<3:1>: Intermediate RTS value used by the Receive SRTS circuitry.
Last Seq (Last Sequence Number): This state variable keeps track of the last sequence number received by the Fast SN Processing SM.
Last Good (Last Good Sequence Number): This state variable keeps track of the last valid or in-sequence sequence number received by the Fast SN
Processing SM.
Fast State: Indicates which state the Fast Sequence Number Processing state machine will enter upon the arrival of the next cell from this VC.
PV_SN<2:0> (Previous Valid Sequence Number): Sequence number of the last valid, in-sync cell received by the SRTS circuitry.
I (Initialized): ‘0’ = VC uninitialized; ‘1’ = VC initialized. Must be initialized to ‘0’ by software.
SDT RX_SAR Write Pointer: Indicates which location will next be written within a Reassembly Circular Buffer.
C (Next CD State): Indicates which state the Correction/Detection state machine will enter upon the arrival of the next cell from this VC. This bit must be ini-
tialized to ‘0’ (Correction).
P (Pointer Reframe Pending): Status bit indicating that a pointer reframe error has occurred and has yet to be compensated for or reported to the MIB. Must
be set to ‘0’ by software.
Pi (Pointer Initialization): Must be set to ‘1’ by software.
Current Frame: This field indicates which frame of the multiframe is currently being received. Used only if VC is carrying CAS data.
Current Entry: Points to the address of the Reassembly Circular Buffer currently being written. Must be initialized to 0Eh.
Location in Structure: This field indicates how many bytes remain before the start of the next AAL1 structure. This field must be set to ‘0’ by software.
MIB Statistics: AAL1 Sequence Errors, AAL1 Header Errors, Misinserted Cells, Lost Cells, Pointer Parity Errors, Pointer Reframes, Buffer Over-
flows, and Buffer Underruns are 8-bit fields for each MIB statistic which must be collected on a per-VC basis. Reassembled Cells is stored in a 16-bit field.
NOTE: The pointer reframe field will usually be incremented to ‘1’ upon the arrival of the first valid pointer.
V (VC Arrival): This bit is set by the SDT RX_SAR each time a cell arrives on this VC. The CPU can clear it to ‘0’ to provide per-VC timeout monitoring.
Cc (CAS Changed): Status bit indicating that at least one CAS nibble in VC has changed since last received CAS value.
Po (Pointer Out-of-Range): Pointer out-of-range error noted if pointer-byte has an invalid value (i.e., > 93 and not a dummy value of 127).
Ro: Status bits which indicate rollovers on MIB status fields. The nine rollover bits correspond to the order of the MIB statistics fields in the control structure:
bit<0> = Reassembled Cell Rollover, bit<1> = AAL1 Header Rollover, etc.
Reassembly Circular Buffer Base Address: This field forms part of the address of a Reassembly Circular Buffer. Refer to Table 18 on page 82 and the
accompanying text for information regarding the addresses of SDT Reassembly Circular Buffers in external memory.
CAS0 - CAS127: Fields containing the four-bit nibbles representing the Channel Associated Signalling for the corresponding channel. These values are trans-
mitted to the TDM module regardless of whether the received VC is configured for CAS. Must be set to initial values by software.
Sequence Number Checking (Correction/Detection State Machine)
Table 12 - Fields within the SDT Reassembly Control Structure
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