MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 123

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.2.3
Address: 1044 (Hex)
Label: TXEN
Reset Value: 0000 (Hex)
Address: 2000 (Hex)
Label: URCR
Reset Value: 00FF (Hex)
Address: 2002 (Hex)
Label: URSER
Reset Value: 0000 (Hex)
LATE_ARRIVALS
UDT_HDR_ROLL
UDT_SEQ_ROLL
UDT_INSERT_
UDT_REASS_
UDT_DUMMY
UDT_LOST_
ROLL_SE
ROLL_SE
Reserved
Reserved
CHECK_
TXENB
Label
Label
LOST
Label
_SE
_SE
UDT RX_SAR Module
Position
Position
Position
15:10
15:1
Bit
7:0
Bit
Bit
8
9
0
1
2
3
0
Table 42 - UDT Reassembly Service Enable Register
Type
Type
Table 41 - UDT Reassembly Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
Type
R/W
R/O
Table 40 - TX_SAR Master Enable Register
UDT RX_SAR Dummy Cell Octet.
This octet is inserted into a port’s UDT Reassembly Circular Buffer 47 times when dummy
cell insertion is required. Defaults to FFh, to represent silence.
UDT Insert Number of Lost Cells Flag.
When set, the number of dummy cells inserted into the UDT Reassembly Circular Buffer in
the case of a multi-cell loss equals the number of lost cells (up to 7). When this bit is
cleared (default), a maximum of 2 dummy cells are inserted in a multi-cell loss case.
Check for Late Cell Arrivals in UDT mode.
When set, this bit causes a dummy cell to be inserted into the UDT Reassembly Circular
Buffer for the corresponding port, if the late cell timeout period for this port is passed while
the port is in “sync”. The late cell timeout period for the port is configured in the port’s
Timeout Configuration Register at 3200h + p*2h. Default value: disabled.
Always reads “0000_00”.
When set, the assertion of the Reassembled Cells Counter Rollover status bit in a UDT
Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the
UDT Reassembly Status Register at 2004h.
When set, the assertion of the AAL1 Header Byte Error Counter Rollover status bit in a
UDT Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in
the UDT Reassembly Status Register at 2004h.
When set, the assertion of the AAL1 Sequence Error Counter Rollover status bit in a UDT
Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the
UDT Reassembly Status Register at 2004h.
When set, the assertion of the Lost Cells Counter Rollover status bit in a UDT Reassembly
Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the UDT
Reassembly Status Register at 2004h.
When cleared, the TX_SAR will not produce UDT or SDT cells for any port.
Always reads “0000_0000_0000_000”.
Zarlink Semiconductor Inc.
MT90520
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Description
Description
Description
Data Sheet