MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 173

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

TX Queuing represents the possible delay due to cell operations queuing in front of the single high-speed TDM
segmentation and cell-assembly engine (TX_SAR). In UDT mode, worst case for this is the time taken to process
27 cells (one for each of the other TDM ports). In SDT mode, worst case for TX Queueing with a porperly
configured control structure is always less than a TDM frame (125 microseconds). This is a variable delay, and the
number given here is the peak, worst-case, low-probability value.
TX Processing is the time required for internal processing and data moves. This is a fixed delay in UDT and SDT
mode.
Physical layer and network delays are the delays due to speed-of-transmission delays in the physical layer,
including transmission time on the UTOPIA bus, and queuing delays at the switches through the network, including
queuing in front of the physical layer devices directly connected to the MT90520. This is in general a variable delay,
and usually represents the largest source of Cell Delay Variation (CDV) that the reassembly path (RX_SAR) has to
deal with.
RX UTOPIA Queuing represents the possible delay due to a burst of cells arriving faster than the RX_SAR can
process them. In UDT mode, the worst case is 27 cells (one for each of the other TDM ports), and in SDT mode the
worst case is always less than 125 microseconds. This is a variable delay.
RX Processing delay is the time required for internal processing and data moves. This is a fixed delay in UDT and
SDT mode.
Pointer Offset represents the random time-offset between segmentation operation at one end of link, and
reassembly operation at the other end of link. In UDT mode this is some fraction of a cell payload assembly period.
In SDT mode this is some fraction of the 125 microsecond TDM frame. This is a static delay, except for wander
difference in the segmentation and reassembly TDM clocks.
CDV Buffering is the delay due to the cell-delay-variation buffer, and is controlled by the setting (per-VC) of the
internal “Maximum Lead” variable. The delay through the CDV buffer is generally one-half of the limit set by the
“Maximum Lead” variable.
Mode
UDT T1
UDT E1
SDT
SDT Trunking
N > 46
RX
UTOPIA
Queuing
(µsec)
min: 0
max: 45.8
min: 0
max: 45.8
min: 0
max: 125
min: 0
max: 125
RX
Processing
(µsec)
1.7
1.7
125
125
Table 106 - Reassembly Latency
Zarlink Semiconductor Inc.
Pointer
Offset
(µsec)
min:0
max: 243.5
min: 0
max: 183.6
min: 0
max: 125
min: 0
max: 125
MT90520
173
CDV Buffering
(µsec)
0.5 X Max_Lead
X 5.18
0.5 X Max_Lead
X 3.91
0.5 X Max_Lead
X 125
0.5 X Max_Lead
X 125
Total RX /
Reassembly
(µsec)
min: 1.7 + 2.59 X Max_Lead
max: 291 + 2.59 X Max_Lead
min: 1.7 + 1.95 X Max_Lead
max: 231.1 + 1.95 X Max_Lead
min: 125 + 62.5 X Max_Lead
max: 375 + 62.5 X Max_Lead
min: 125 + 62.5 X Max_Lead
max: 375 + 62.5 X Max_Lead
Data Sheet