MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 124

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 2002 (Hex)
Label: URSER
Reset Value: 0000 (Hex)
UDT_LATE_ROLL
Address: 2004 (Hex)
Label: URSR
Reset Value: 001F (Hex)
Address: 2006 (Hex)
Label: URCCR
Reset Value: 0000 (Hex)
UDT_MIS_ROLL_
CELL_COUNTER
CELL_COUNTER
UDT_RXSAR_SE
CELL_COUNTER
SERVICE_PORT
UDT_UNDER_
_RO_STATUS
UDT_RXSAR_
UDT_OVER_
ROLL_SE
ROLL_SE
Reserved
Reserved
_RO_SE
STATUS
Label
Label
Label
_SE
SE
Position
Position
Position
15:8
11:5
15:0
4:0
Bit
Bit
Bit
12
13
14
15
4
5
6
7
Table 42 - UDT Reassembly Service Enable Register
Table 44 - UDT Reassembly Cell Counter Register
R/O/L
R/O/L
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/O
R/O
Table 43 - UDT Reassembly Status Register
When set, the assertion of the Misinserted Cells Counter Rollover status bit in a UDT
Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the
UDT Reassembly Status Register at 2004h.
When set, the assertion of the Buffer Underrun Counter Rollover status bit in a UDT
Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the
UDT Reassembly Status Register at 2004h.
When set, the assertion of the Buffer Overrun Counter Rollover status bit in a UDT
Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the
UDT Reassembly Status Register at 2004h.
When set, the assertion of the Late Cells Counter Rollover status bit in a UDT Reassembly
Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the UDT
Reassembly Status Register at 2004h.
Always reads “0000_0000”.
TDM port associated with the last UDT Reassembly Control Structure to generate a
serviceable event (i.e., a control structure status field rollover). Defaults to 1Fh (illegal
port) and returns to 1Fh when the UDT_RXSAR_STATUS bit in this register is
cleared.
Always reads “0000_000”.
UDT RX_SAR Cell Counter Rollover Service Enable
When set, a ‘1’ on CELL_COUNTER_RO_STATUS in this register will cause the
UDT_RXSAR_SRV bit to be set in the Main Status Register at 0002h.
If set, indicates that the UDT RX_SAR Cell Counter located in register 2006h has
overflowed.
UDT RX_SAR Service Enable.
When set, a ‘1’ on UDT_RXSAR_STATUS in this register will cause the
UDT_RXSAR_SRV bit to be set in the Main Status Register at 0002h.
If set, indicates that an unmasked (due to settings of the Service Enable bits in the UDT
Reassembly Service Enable Register at 2002h) UDT RX_SAR serviceable event has
occurred. Writing a ‘0’ to this bit clears it and sets SERVICE_PORT to 1Fh.
Number of cells received by the UDT RX_SAR.
Zarlink Semiconductor Inc.
MT90520
124
Description
Description
Description
Data Sheet