ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet
ZL50114GAG2
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ZL50114GAG2 Summary of contents
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... Channel CESoP ZL50110GAG ZL50111GAG ZL50114GAG ZL50110GAG2 552 PBGA** Trays, Bake & Drypack ZL50111GAG2 ZL50114GAG2 552 PBGA** Trays, Bake & Drypack • Direct connection to LIUs, framers, backplanes • Dual reference Stratum 3, 4 and 4E DPLL for synchronous operation Network Interfaces • ...
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Packet Processing Functions • Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413., IETF CESoPSN, IETF SAToP and user programmable • Packet re-sequencing to allow lost packet detection • Four classes of service with programmable priority mechanisms ...
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Description The ZL50110/11/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The ZL50110/11/14 provides both structured and unstructured circuit emulation services over packet (CESoP) for T1 and 8 J2 streams across ...
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Device Line Up There are three products within the ZL50110/11/14 family, with capacity as shown in the following table: Device TDM Interfaces ZL50114 4 T1 streams or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 ...
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Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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External Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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JTAG Interface Timing ...
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Figure 1 - ZL50110/11/14 High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 49 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Capacity of Devices in the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Changes Summary The following table captures the changes from the February 2006 issue. Page Item 86 Table 38, Table 38 - External Memory Timing The following table captures the changes from the April 2005 issue. Page Item 41, 42 ...
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Physical Specification The ZL50111 will be packaged in a PBGA device. Features: • Body Size: • Ball Count: • Ball Pitch: • Ball Matrix: • Ball Diameter: • Total Package Thickness: The ZL50110 will be packaged in a PBGA ...
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ZL50111 Package view from TOP side. Note that ball A1 is non-chamfered corner ...
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ZL50110 Package view from TOP side. Note that ball A1 is non-chamfered corner ...
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ZL50114 Package view from TOP side. Note that ball A1 is non-chamfered corner ...
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Ball Signal Assignment Ball Signal Name Number A1 GND A2 TDM_STo[1] A3 TDM_CLKo[3] ‡ A4 TDM_STo[4] ‡ A5 TDM_STo[5] ‡ A6 TDM_STi[6] ‡ A7 TDM_STo[7] ‡ A8 TDM_STi[7] † A9 TDM_CLKo[10] † A10 TDM_CLKi[10] † A11 TDM_CLKi[11] † A12 TDM_CLKo[13] ...
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Ball Signal Name Number † E16 TDM_CLKi[19] † E17 TDM_STo[23] † E18 TDM_STi[23] † E19 TDM_CLKi[25] † E20 TDM_STi[26] † E21 TDM_CLKi[28] E22 GND † E23 TDM_CLKo[30] † E24 TDM_CLKi[30] † E25 TDM_STi[30] † E26 TDM_STo[29] F1 RAM_DATA[15] F2 RAM_DATA[13] ...
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Ball Signal Name Number M4 RAM_ADDR[3] M5 RAM_ADDR[0] M6 RAM_ADDR[1] M9 VDD_IO M11 GND M12 GND M13 GND M14 GND M15 GND M16 GND M18 VDD_IO M21 VDD_CORE M22 M1_REFCLK M23 M1_RXCLK M24 M1_RXD[5] M25 M1_RXD[7] M26 M1_RXDV N1 GND ...
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Ball Signal Name Number V12 VDD_IO V13 VDD_IO V14 VDD_IO V15 VDD_IO V16 VDD_IO V17 VDD_IO V18 VDD_IO V21 M0_TXD[7] V22 M0_TXER V23 M0_TXEN V24 M0_RXD[4] V25 M0_RXDV V26 M0_RXER W1 RAM_BW_E W2 RAM_BW_G W3 GPIO[0] W4 GPIO[3] W5 GPIO[9] ...
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Ball Signal Name Number AD6 RAM_DATA[58] AD7 RAM_DATA[63] AD8 JTAG_TCK AD9 IC_GND AD10 CPU_ADDR[7] AD11 CPU_ADDR[11] AD12 CPU_ADDR[17] AD13 CPU_ADDR[21] AD14 CPU_WE AD15 CPU_SDACK2 AD16 CPU_IREQ1 AD17 CPU_DATA[3] AD18 CPU_DATA[6] AD19 CPU_DATA[14] AD20 CPU_DATA[20] AD21 CPU_DATA[24] AD22 CPU_DATA[29] † AD23 ...
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External Interface Description The following key applies to all tables: I Input O Output D Internal 100 kΩ pull-down resistor present U Internal 100 kΩ pull-up resistor present T Tri-state Output 3.1 TDM Interface All TDM Interface signals are ...
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Signal I/O TDM_STo[31:0] OT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] TDM_CLKi[31: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] Table ...
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Signal I/O TDM_CLKo[31:0] O [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] Table 2 - TDM Interface ZL50111 Stream Pin Definition (continued) Note: Speed modes: 2.048 Mbps - all 32 streams active ...
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ZL50110 Variant TDM stream connection Signal I/O TDM_STi[7: [7] [6] [5] [4] [3] [2] [1] [0] TDM_STo[7:0] OT [7] [6] [5] [4] [3] [2] [1] [0] TDM_CLKi[7: [7] [6] [5] [4] [3] [2] [1] [0] ...
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ZL50114 Variant TDM Stream Connection Signal I/O TDM_STi[3: [3] [2] [1] [0] TDM_STo[3:0] OT [3] [2] [1] [0] TDM_CLKi[3: [3] [2] [1] [0] TDM_CLKo[3:0] OT [3] [2] [1] [0] Table 4 - TDM Interface ZL50114 ...
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TDM Signals Common to ZL50111, ZL50110 and ZL50114 Signal I/O TDM_CLKi_REF TDM_CLKo_REF O E6 TDM_FRMi_REF TDM_FRMo_REF O B1 Table 5 - TDM Interface Common Pin Definition ZL50110/11/14 Package Balls TDM port reference clock ...
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PAC Interface All PAC Interface signals are 5 V tolerant All PAC Interface outputs are high impedance while System Reset is LOW. Signal I/O TDM_CLKiP TDM_CLKiS PLL_PRI OT U1 PLL_SEC OT V1 Table ...
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Packet Interfaces For the ZL50111 variant the packet interface is capable of either 3 MII interfaces, 2 GMII interfaces or 2 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an integrated 1000BASE-X PCS module. ...
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Signal I/O M_MDC O H23 M_MDIO ID/ G26 OT Table 8 - MII Management Interface Package Ball Definition Signal I/O M0_LINKUP_LED O G24 on ZL50110/4 AB23 on ZL50111 M0_ACTIVE_LED O AC26 M0_GIGABIT_LED O H22 M0_REFCLK I D AA24 M0_RXCLK I ...
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Signal I/O M0_RBC0 I U Y24 M0_RBC1 I U AA25 M0_COL I D Y25 M0_RXD[7: [7] [6] [5] [4] M0_RXDV / I D V25 M0_RXD[8] M0_RXER / I D V26 M0_RXD[9] Table 9 - MII Port 0 Interface ...
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Signal I/O M0_CRS / I D U25 M0_Signal_Detect M0_TXCLK I U U24 M0_TXD[7:0] O [7] [6] [5] [4] M0_TXEN / O V23 M0_TXD[8] M0_TXER / O V22 M0_TXD[9] M0_GTX_CLK O U21 Table 9 - MII Port 0 Interface Package Ball ...
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Signal I/O M1_LINKUP_LED O G23 on ZL50110/4 F26 on ZL50111 M1_ACTIVE_LED O AB25 M1_GIGABIT_LED O G25 M1_REFCLK I D M22 M1_RXCLK I U M23 M1_RBC0 I U U26 M1_RBC1 I U T25 M1_COL I D R25 Table 10 - MII ...
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Signal I/O M1_RXD[7: [7] [6] [5] [4] M1_RXDV / I D M26 M1_RXD[8] M1_RXER / I D L21 M1_RXD[9] M1_CRS / I D L23 M1_Signal_Detect M1_TXCLK I U L22 M1_TXD[7:0] O [7] [6] [5] [4] M1_TXEN / O ...
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Signal I/O M1_TXER / O N23 M1_TXD[9] M1_GTX_CLK O N21 Table 10 - MII Port 1 Interface Package Ball Definition (continued) Note: This port must not be used to receive data at the same time as port 3, Signal I/O ...
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Note: This port must not be used to receive data at the same time as port 3, Signal I/O M2_RXER I D AC24 M2_CRS I D AC25 M2_TXCLK I U AD26 M2_TXD[3:0] O [3] [2] M2_TXEN O AC22 M2_TXER O ...
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Note: This port must not be used to receive data at the same time as port 2, Signal I/O M3_RXCLK I U K26 M3_COL I D J26 M3_RXD[3: [3] [2] M3_RXDV I D J21 M3_RXER I D H26 ...
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External Memory Interface All External Memory Interface signals are 5 V tolerant. All External Memory Interface outputs are high impedance while System Reset is LOW. If the External Memory Interface is unused, all input pins may be left unconnected. ...
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Signal I/O RAM_ADDR[19:0] O [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] RAM_BW_A RAM_BW_B RAM_BW_C RAM_BW_D RAM_BW_E RAM_BW_F RAM_BW_G RAM_BW_H RAM_RW# O ...
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CPU Interface All CPU Interface signals are 5 V tolerant. All CPU Interface outputs are high impedance while System Reset is LOW. Signal I/O CPU_DATA[31: CPU_ADDR[23:2] I CPU_CS I U CPU_WE I Table 14 - CPU Interface ...
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Signal I/O CPU_OE I CPU_TS_ALE I CPU_SDACK1 I CPU_SDACK2 I CPU_CLK I CPU_TA OT Table 14 - CPU Interface Package Ball Definition (continued) ZL50110/11/14 Package Balls AE14 AE15 AF15 AD15 AC14 AB14 40 Zarlink Semiconductor Inc. Data Sheet Description CPU ...
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Signal I/O CPU_DREQ0 OT CPU_DREQ1 OT CPU_IREQO O CPU_IREQ1 O Table 14 - CPU Interface Package Ball Definition (continued) 3.6 System Function Interface All System Function Interface signals are 5 V tolerant. The core of the chip will be held ...
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Test Facilities 3.7.1 Administration, Control and Test Interface All Administration, Control and Test Interface signals are 5 V tolerant. Signal I/O GPIO[15:0] ID/ [15] [14] OT [13] [12] [11] [10] [9] [8] TEST_MODE[2: [2] [1] [0] Table ...
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Miscellaneous Inputs Signal IC_GND AD9, AF8, R5, T4, AE8 IC_VDD_IO AF16 Table 18 - Miscellaneous Inputs Package Ball Definitions 3.9 Power and Ground Connections Signal VDD_IO J9 J13 J17 V11 V15 GND A1 F6 L11 ...
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Internal Connections Signal IC R6, AC16, AE17 4.0 Typical Applications 4.1 Leased Line Provision Circuit emulation is typically used to support the provision of leased line services to customers using legacy TDM equipment. For example, Figure 5 shows a ...
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Multi-Tenant Units T1/E1 Links Figure 6 - Metropolitan Area Network Aggregation using CESoP 4.3 Digital Loop Carrier The Broadband Digital Loop Carrier (BBDLC) application, shown in Figure 7, consists of a BBDLC connected to the Central Office (CO ...
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Remote Concentrator The remote concentrator application, shown in Figure 8, consists of a remote concentrators connected to the Central Office (CO dedicated fiber link running Gigabit Ethernet (GE) or Ethernet over SONET (EoS) rather than by NxT1/E1 ...
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Each T1/E1 may be asynchronous should a service provider be backhauling T1/E1s from multiple carriers. Co-Located Base Stations ATM over 3G T1/E1 Base Station ATM over 2.5G T1/E1 Base Station TDM over 2G T1/E1 Base ...
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T1/E1 LIUs T1/E1 or 1024 Channel T1/E1 LIUs Voice and Ethernet Data Traffic Services Unstructured, Asynchronous CES Unstructured, Asynchronous CES T3/E3 or T1/E1 LIU T1/ T3/E3 T3/E3 or T1/E1 LIU Figure 10 ...
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Block Diagram A diagram of the ZL50110/11/14 device is given in Figure 12, which shows the major data flows between functional components. TDM Interface Clock Recovery Data Flows Control Flows Figure 12 - ZL50110/11/14 Data and Control Flows 5.2 ...
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Flow Number This flow is for loopback test purposes only Each of the 11 data flows uses the Task Manager to route packet information to the next block or interface for onward transmission. This section describes the ...
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Unstructured data is treated asynchronously, with every stream using its own clock. Clock recovery is provided on each output stream, to reproduce the TDM service frequency at the egress of the packet network. Structured data is treated synchronously, i.e., all ...
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TDM Clock Structure The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for unstructured TDM data. The ZL50110/11/14 is capable of providing the TDM clock for either of the modes. The ZL50110/11/14 supports ...
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Structured Payload Operation In structured mode a context may contain any number of 64 kbps channels. These channels need not be contiguous and they may be selected from any input stream. Channels may be added or deleted dynamically from ...
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Structured Payload Order Packets are assembled sequentially, with each channel placed into the packet as it arrives at the TDM Access Interface. A fixed order of channels is maintained (see Figure 15), with channel 0 placed before channel 1, ...
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Protocol Engine In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the ...
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Clock Recovery One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked into the central office reference clock, and hence may be any value within the tolerance ...
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Adaptive Clock Recovery For applications where there is no common reference clock between provider edge units, an adaptive clock recovery technique is provided. This infers the clock rate of the original TDM service clock from the mean arrival rate ...
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System Features 7.1 Latency The following lists the intrinsic processing latency of the ZL50110/11/14, regardless of the number of active channels or contexts. TDM to Packet transmission processing latency less than 125 µs • Packet to TDM transmission processing ...
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Loss of Service (LOS) During normal operation, a situation may arise where a Loss of Service occurs. This may be caused by a disruption in the transmission line due to engineering works or cable disconnection, for example. The locally ...
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External Memory Requirements for different packet sizes 8 T1 streams, with Ethernet/MPLS/MPLS/RTP/CESoPSN headers 8192 7168 6144 5120 4096 3072 2048 1024 Figure 20 - External Memory Requirement for ZL50110 7.6 GIGABIT Ethernet - Recommended Configurations NOTE: In ...
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Central Ethernet Switch GMII GMII ZL5011x TDM Figure 21 - Gigabit Ethernet Connection - Central Ethernet Switch TDM data and control packets are directed to the appropriate ZL50110/11/14 device through the Ethernet Switch. There is no limit on the ...
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Redundant Ethernet Switch GMII GMII ZL5011x TDM Figure 22 - Gigabit Ethernet Connection - Redundant Ethernet Switch The central Ethernet Switch configuration can be extended to include a redundant switch connected to the second ZL50110/11/14 GMII port. One port ...
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RST SCLK 7.8 JTAG Interface and Board Level Test Features The JTAG interface is used to access the boundary scan logic for board level production testing. 7.9 External Component Requirements • Direct connection to PowerQUICC™ ...
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Test Modes Operation 7.11.1 Overview The ZL50110/11/14 family supports the following modes of operation. 7.11.1.1 System Normal Mode This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this mode via ...
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DPLL Specification The ZL50110/11/14 family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 3 and Stratum 4/4E requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the jitter/wander tolerance, jitter/wander transfer, ...
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The maximum lock-in range can be programmed up to ±372 ppm regardless of the input frequency. The DPLL will fail to lock if the source input frequency is absent not of approximately the correct frequency or if ...
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The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the event of an invalid signal regardless of mode. 8.3 Locking Mode Reference Switching When the reference source the DPLL is currently ...
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DPLL Loop Filter • DPLL Limiter (phase slope) Although a short phase lock time is desirable not always achievable due to other synchroniser requirements. For instance, better jitter transfer performance is obtained with a lower frequency loop ...
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Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and ...
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Memory Map and Register Definitions All memory map and register definitions are included in the ZL50110/11/14 Programmers Model document. ZL50110/11/14 Figure 25 - Jitter Transfer Function - Detail 70 Zarlink Semiconductor Inc. Data Sheet ...
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DC Characteristics Absolute Maximum Ratings* Parameter I/O Supply Voltage Core Supply Voltage PLL Supply Voltage Input Voltage Input Voltage (5 V tolerant inputs) Continuous current at digital inputs Continuous current at digital outputs Package power dissipation Storage Temperature * ...
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DC Electrical Characteristics - Typical characteristics are at 1.8 V core, 3.3 V I/O, 25°C and typical processing. The min. and max. values are defined over all process conditions, from -40 to 125°C junction temperature, core voltage 1.65 to 1.95 ...
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AC Characteristics 11.1 TDM Interface Timing - ST-BUS The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device sourcing the data, or Master mode, where the TDM clocks are ...
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In synchronous mode the clock must be within the locking range of the DPLL to function correctly (± 245 ppm). In asynchronous mode, the clock may be any frequency. Channel 127 bit 1 TDM_CKLI TDM_F0i t t STIS TDM_STi TDM_STo ...
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ST-BUS Master Clock Mode Data Format Parameter ST-BUS TDM_CLKo Period 8.192 Mbps TDM_CLKo High mode TDM_CLKo Low ST-BUS TDM_CLKo Period 2.048 Mbps TDM_CLKo High mode TDM_CLKo Low All Modes TDM_F0o Delay TDM_STo Delay Active-Active TDM_STo Delay Active to HiZ ...
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Channel 31 Bit 0 TDM_CLKO (2.048 MHz) TDM_CLKO (4.096 MHz) TDM_F0o TDM_STi TDM_STo Figure 29 - TDM Bus Master Mode Timing at 2.048 Mbps 11.2 TDM Interface Timing - H.110 Mode These parameters are based on the H.110 Specification from ...
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Ts 127 Bit 8 TDM_C8 TDM_FRAME TDM_D Input Ts 127 Bit 8 TDM_D Output 11.3 TDM Interface Timing - H-MVIP These parameters are based on the Multi-Vendor Integration Protocol (MVIP) specification for an H-MVIP Bus, Release 1.1a (1997). Positive transitions ...
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Parameter TDM_F0 width TDM_F0 setup TDM_F0 hold Table 29 - TDM H-MVIP Timing Specification (continued) Ts 127 Bit 7 TDM_C16 TDM_F0 TDM_HDS Input TDM_HDS Output Ch 127 Bit 7 Figure 31 - TDM - H-MVIP Timing Diagram for 16 MHz ...
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TDM_TXCLK TDM_TXDATA TDM_RXCLK TDM_RXDATA Figure 32 - TDM-LIU Structured Transmission/Reception 11.5 PAC Interface Timing Parameter TDM_CLKiP High / Low Pulsewidth TDM_CLKiS High / Low Pulsewidth 11.6 Packet Interface Timing Data for the MII/GMII/TBI packet switching is based on Specification IEEE ...
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Parameter TXCLK to TXER active delay (TXCLK rising edge) Table 32 - MII Transmit Timing - 100 Mbps TXCLK t EV TXEN t DV TXD[3:0] TXER 11.6.2 MII Receive Timing Parameter RXCLK period RXCLK high wide time RXCLK low wide ...
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RXCLK RXDV RXD[3:0] RXER Figure 34 - MII Receive Timing Diagram ZL50110/11/ DVS ERH t ERS 81 Zarlink Semiconductor Inc. Data Sheet t t CLO CHI t DVH ...
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GMII Transmit Timing Parameter GTXCLK period GTXCLK high time GTXCLK low time GTXCLK rise time GTXCLK fall time GTXCLK rise to TXD[7:0] active delay GTXCLK rise to TXEN active delay GTXCLK rise to TXER active delay Table 34 - ...
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GMII Receive Timing Parameter RXCLK period RXCLK high wide time RXCLK low wide time RXCLK rise time RXCLK fall time RXD[7:0] setup time (RXCLK rising edge) RXD[7:0] hold time (RXCLK rising edge) RXDV setup time (RXCLK rising edge) RXDV ...
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TBI Interface Timing Parameter GTXCLK period GTXCLK high wide time GTXCLK low wide time TXD[9:0] Output Delay (GTXCLK rising edge) RCB0/RBC1 period RCB0/RBC1 high wide time RCB0/RBC1 low wide time RCB0/RBC1 rise time RCB0/RBC1 fall time RXD[9:0] setup time ...
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RBC1 RBC0 RXD[9:0] /I/ /S/ /D/ /D/ /D/ Signal_Detect 11.6.6 Management Interface Timing The management interface is common for all inputs and consists of a serial data I/O line and a clock line. Parameter M_MDC Clock Output period M_MDC high ...
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M_MDC M_MDIO Figure 40 - Management Interface Timing for Ethernet Port - Write 11.7 External Memory Interface Timing The timings for the External Memory Interface are based on the requirements of a ZBT-SRAM device, with the system clock speed at ...
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CPU Interface Timing Parameter CPU_CLK Period CPU_CLK High Time CPU_CLK Low Time CPU_CLK Rise Time CPU_CLK Fall Time CPU_ADDR[23:2] Setup Time CPU_ADDR[23:2] Hold Time CPU_DATA[31:0] Setup Time CPU_DATA[31:0] Hold Time CPU_CS Setup Time CPU_CS Hold Time CPU_WE/CPU_OE Setup Time ...
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CPU_CLK t CAS CPU_ADDR[23:2] t CSS CPU_CS CPU_OE CPU_WE t CTS CPU_TS_ALE t SDV CPU_DATA[31:0] CPU_TA NOTE: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS and CPU_OE are asserted. CPU_TA will continue to be ...
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CPU_CLK t CWV CPU_DREQ1 CPU_SDACK2 CPU_CS CPU_OE CPU_WE CPU_TS_ALE CPU_DATA[31:0] CPU_TA Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid when CPU_TA is asserted (always timed as shown). ...
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System Function Port Parameter SYSTEM_CLK Frequency SYSTEM_CLK accuracy (synchronous master mode) SYSTEM_CLK accuracy (synchronous slave mode and asynchronous mode) Note 1: The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for ...
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JTAG Interface Timing Parameter JTAG_CLK period JTAG_CLK clock pulse width JTAG_CLK rise and fall time JTAG_TRST setup time JTAG_TRST assert time Input data setup time Input Data hold time JTAG_CLK to Output data valid JTAG_CLK to Output data high ...
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HIGH JTAG_TCK t TPH t TPSU JTAG_TMS JTAG_TDI Don't Care HiZ JTAG_TDO Figure 46 - JTAG Signal Timing JTAG_TCK JTAG_TRST Figure 47 - JTAG Clock and Reset Timing ZL50110/11/14 LOW t JCP t TPSU t TOPDV t t ...
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Power Characteristics The following graph in Figure 48 illustrates typical power consumption figures for the ZL50110/11/14 family. Typical characteristics are at 1.8V core, 3.3V I/O, 25°C and typical processing. Power is plotted against the number of active contexts, which ...
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Design and Layout Guidelines This guide will provide information and guidance for PCB layouts when using the ZL50110/11/14. Specific areas of guidance are: • High Speed Clock and Data, Outputs and Inputs • CPU_TA Output 13.1 High Speed Clock ...
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External Memory Interface - special considerations during layout The timing of address, data and control are all related to the system clock which is also used by the external SSRAM to clock these signals. Therefore the propagation delay of ...
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CPU_TA from ZL50110/11/14 CPU_CLK to ZL50110/11/14 The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be fitted to ensure correct operation of the TA input to the processor. ...
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To generate a pin for pin compatible PCB for all three variants, the following stuffing options may be used as shown in Figure 50. For the ZL50111 variant, resistors R4 and R6 are not populated. For the ZL50110 and ZL50114 ...
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Table 43 lists the various components that are used for each variant. Component LED M1 LED M2 LED M3 LED Table 43 - Mx_LINKUP_LED Stuffing Option ZL50110/11/14 ZL50111 √ √ √ - √ ...
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Reference Documents 14.1 External Standards/Specifications • IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture • IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer • ECTF H.110 Revision 1.0; Hardware Compatibility Specification • ...
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Glossary API Application Program Interface ATM Asynchronous Transfer Mode CDP Context Descriptor Protocol (the protocol used by Zarlink’s MT9088x family of TDM-Packet devices) CESoP Circuit Emulation Services over Packet CESoPSN Circuit Emulation Services over Packet Switched Networks (draft-ietf-pwe3-cesopsn) CONTEXT ...
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PSTN Public Switched Telephone Circuit PTX Packet Transmit PWE3 Pseudo-Wire Emulation Edge to Edge (a working group of the IETF) QOS Quality of Service RTP Real Time Protocol (RFC 1889) PE Protocol Engine SAToP Structure-Agnostic Transport over Packet SSRAM Synchronous ...
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Zarlink Semiconductor 2003 All rights reserved ISSUE 213837 ACN DATE 12Dec02 19Aug03 APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...