ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 68

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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Although a short phase lock time is desirable, it is not always achievable due to other synchroniser requirements.
For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking
time; and a better (smaller) phase slope performance will increase locking time. Additionally, the locking time is
dependent on the p_shift value.
The DPLL Loop Filter and Limiter have been optimised to meet the Telcordia GR-1244-CORE jitter transfer and
phase alignment speed requirements. The phase lock time is guaranteed to be no greater than 30 seconds when
using the recommended Stratum 3 and Stratum 4/4E register settings.
8.6
The DPLL has a Lock Status Indicator and a corresponding Lock Change Interrupt. The response of the Lock
Status Indicator is a function of the programmed Lock Detect Interval (LDI) and Lock Detect Threshold (LDT) values
in the dpll_ldetect register. The LDT register can be programmed to set the jitter tolerance level of the Lock Status
Indicator. To determine if the DPLL has achieved lock the Lock Status Indicator must be high for a period of at least
30 seconds. When the DPLL loses lock the Lock Status Indicator will go low after LDI x 125 µs.
8.7
The DPLL is designed to withstand, and improve inherent jitter in the TDM clock domain.
8.7.1
For T1(1.544 MHz), E1(2.048 MHz) and J2(6.312 MHz) input frequencies, the DPLL will accept a wander of up to
±1023UI
down output for T3/E3) input frequencies, the wander acceptance is limited to ±1 UI (0.1 Hz). This principle is
illustrated in Table 26.
8.7.2
Intrinsic jitter is the jitter produced by a synchronizer and measured at its output. It is measured by applying a jitter
free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured
when the device is in a non synchronizing mode such as free running or holdover, by measuring the output jitter of
the device. Intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable
standards.
The intrinsic jitter in the DPLL is reduced to less than 1 ns p-p
can be programmed so that the output clock meets all the Stratum 3 requirements of Telcordia GR-1244-CORE.
Stratum 4/4E is also supported.
8.7.3
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e. remain in lock and/or
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards.
The DPLL’s jitter tolerance can be programmed to meet Telcordia GR-1244-CORE DS1 reference input jitter
tolerance requirements.
1. There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter up to 1 master
clock period is possible, i.e. 10 ns p-p. b) In holdover mode, if a huge amount of jitter had been present prior to entering holdover, then an
additional 2 ns p-p is possible.
DPLL Loop Filter
DPLL Limiter (phase slope)
Lock Status
Jitter
pp
Acceptance of Input Wander
Intrinsic Jitter
Jitter Tolerance
at 0.1 Hz to conform with the relevant specifications. For the 8 kHz (frame rate) and 64 kHz (the divided
Zarlink Semiconductor Inc.
ZL50110/11/14
68
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by an internal Tapped Delay Line (TDL). The DPLL
Data Sheet