ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 94

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.0
This guide will provide information and guidance for PCB layouts when using the ZL50110/11/14. Specific areas of
guidance are:
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13.1
On the ZL50110/11/14 series of devices there are four high-speed data interfaces that need consideration when
laying out a PCB to ensure correct termination of traces and the reduction of crosstalk noise. The interfaces being:
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It is recommended that the outputs are suitably terminated using a series termination through a resistor as close to
the output pin as possible. The purpose of the series termination resistor is to reduce reflections on the line. The
value of the series termination and the length of trace the output can drive will depend on the driver output
impedance, the characteristic impedance of the PCB trace (recommend 50 ohm), the distributed trace capacitance
and the load capacitance. As a general rule of thumb, if the trace length is less than 1/6th of the equivalent length of
the rise and fall times, then a series termination may not be required.
For example:
Typical FR4 board delay = 6.8 ps/mm
Typical rise/fall time for a ZL50110/11/14 output = 2.5 ns
Therefore tracks longer than 61 mm will require termination.
As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is
crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace and therefore it
should be minimised in the layout. The voltage that the external fields cause is proportional to the strength of the
field and the length of the trace exposed to the field. Therefore to minimise the effect of crosstalk some basic
guidelines should be followed.
First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the
coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another
layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or
by placing guard traces between the signals usually held ground potential.
Particular effort should be made to minimise crosstalk from ZL50110/11/14 outputs and ensuring fast rise time to
these inputs.
In Summary:
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High Speed Clock and Data, Outputs and Inputs
CPU_TA Output
External Memory Interface
GMAC Interfaces
TDM Interface
CPU Interface
Place series termination resistors as close to the pins as possible
Minimise output capacitance
Keep common interface traces close to the same length to avoid skew
Protect input clocks and signals from crosstalk
High Speed Clock & Data Interfaces
Design and Layout Guidelines
the equivalent length of rise time = rise time (ps) / delay (ps/mm)
critical track length = (1/6) x (2500/6.8) = 61 mm
Zarlink Semiconductor Inc.
ZL50110/11/14
94
Data Sheet