ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 75

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.1.2
ST-BUS
8.192 Mbps
mode
ST-BUS
2.048 Mbps
mode
All Modes
Data Format
TDM_CLKO
ST-BUS Master Clock Mode
TDM_STo
TDM_F0o
TDM_STi
TDM_CLKo Period
TDM_CLKo High
TDM_CLKo Low
TDM_CLKo Period
TDM_CLKo High
TDM_CLKo Low
TDM_F0o Delay
TDM_STo Delay
Active-Active
TDM_STo Delay
Active to HiZ and
HiZ to Active
TDM_STi Setup Time
TDM_STi Hold Time
Channel 127 Bit 0
Parameter
Figure 28 - TDM Bus Master Mode Timing at 8.192 Mbps
Table 27 - TDM ST-BUS Master Timing Specification
t
STIS
t
Ch 127 Bit 0
STIH
B0
t
FOD
Symbol
t
t
t
t
DZ
Zarlink Semiconductor Inc.
ZL50110/11/14
C16OH
t
t
t
C16OP
t
C16OL
t
t
C4OP
C4OH
t
STOD
C4OL
STIH
FOD
STIS
, t
ZD
t
C16OP
t
STOD
75
Channel 0 Bit 7
237.0
115.0
115.0
Min.
54.0
23.0
23.0
5
5
-
-
-
t
FOD
t
STIS
t
Ch 0 Bit 7
STIH
244.1
Typ.
61.0
B7
-
-
-
-
-
-
-
-
-
251.0
129.0
129.0
Max.
68.0
37.0
37.0
25
33
5
-
-
Channel 0 Bit 6
t
Units
STOD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ch 0 Bit 6
With respect to
TDM_CLKo
falling edge
With respect to
TDM_CLKo
falling edge
With respect to
TDM_CLKo
falling edge
With respect to
TDM_CLKo
With respect to
TDM_CLKo
Data Sheet
Notes
B6