HYS64T128020EDL-2.5-C QIMONDA [Qimonda AG], HYS64T128020EDL-2.5-C Datasheet - Page 17

• Manufacturer Part Number: HYS64T128020EDL-2.5-C
• Description: 200-Pin SO-DIMM DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3.2
Timing Parameters for: DDR2–800
Rev. 1.0, 2007-03
11212006-D34H-5W6Z
Parameter
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated DQ signals
DQS latching rising transition to associated clock
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CK half pulse width
Data-out high-impedance time from CK / CK
Address and control input hold time
Control & address input pulse width for each input
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
Component AC Timing Parameters
(Table
15), DDR2–667
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH.AVG
CK.AVG
CKE
CL.AVG
DAL
DELAY
DH.BASE
DIPW
DQSCK
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DSH
DSS
FAW
FAW
HP
HZ
IH.BASE
IPW
IS.BASE
LZ.DQ
LZ.DQS
MOD
MRD
OIT
QH
(Table
17
16) and DDR2–533C
DDR2–800
–400
2
0.48
2500
3
0.48
WR +
t
t
125
0.35
–350
0.35
0.35
—
– 0.25
50
0.2
0.2
35
45
Min (
t
—
250
0.6
175
2 x
t
0
2
0
t
Min.
IS
IH
CL.ABS
AC.MIN
HP
+
–
t
AC.MIN
t
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
t
CK .AVG
t
CH.ABS
)
QHS
t
nRP
,
+
+400
—
0.52
8000
—
0.52
––
—
+350
—
—
––
—
—
—
—
—
—
—
12
—
12
Max.
—
––
200
+ 0.25
__
t
t
t
—
AC.MAX
AC.MAX
AC.MAX
SO-DIMM DDR2 SDRAM Module
(Table
17)
Unit
ps
nCK
t
ps
nCK
t
nCK
ns
ps
t
ps
t
t
ps
t
ps
t
t
ns
ns
ps
ps
ps
t
ps
ps
ps
ns
nCK
ns
ps
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Internet Data Sheet
TABLE 15
Note
8)
9)
—
10)11)
10)11)
12)
10)11)
13)14)
19)20)15)
—
9)
—
—
16)
17)
18)19)20)
17)
17)
31)
31)
21)
9)22)
23)25)
—
24)25)
9)22)
9)22)
31)
—
31)
26)
1)2)3)4)5)6)7)