HYS64T128021GDL-37-A INFINEON [Infineon Technologies AG], HYS64T128021GDL-37-A Datasheet - Page 14

• Manufacturer Part Number: HYS64T128021GDL-37-A
• Description: 200-Pin Small Outline Dual-In-Line Memory Module
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 8
Symbol
CK[1:0],
CK[1:0]
CKE[1:0]
RAS, CAS,
WE
BA[1:0]
ODT[1:0]
A[9:0],
A10/AP,
A[13:11]
DQ[63:0]
DM[7:0]
DQS[7:0],
DQS[7:0]
V
V
SDA
SCL
SA[1:0]
Data Sheet
S[1:0]
DD
DDSPD
,
,
V
SS
Input/Output Functional Description
Type
I
I
I
I
I
I
I
I/O
I
I/O
Supply —
I/O
I
I
Polarity Function
Cross
point
Active
High
Active
Low
Active
Low
—
Active
High
—
—
Active
High
Cross
point
—
—
—
Address pins used to select the Serial Presence Detect base address.
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down Mode
or the Self Refresh Mode.
Enables the associated DDR2 SDRAM command decoder when low and
disables the command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank 0
is selected by S0; Rank 1 is selected by S1.
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
Selects internal SDRAM memory bank
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA[1:0] to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA[1:0] inputs. If AP is low, then BA[1:0] are used to
define which bank to precharge.
Data Input/Output pins
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is low but blocks
the write operation if it is high. In Read mode, DM lines have no effect
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to
resistor
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from SDA to
a pull-up.
This signal is used to clock data into and out of the SPD EEPROM.
and DDR2 SDRAM mode registers programmed appropriately.
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
14
V
V
DDSPD
SS
through a 20 ohm to 10 Kohm
on the motherboard to act as
512 Mbit DDR2 SDRAM
09122003-FTXN-KM26
Rev. 0.91, 2004-06
Overview
.