HYS64V2100GCU-10 SIEMENS [Siemens Semiconductor Group], HYS64V2100GCU-10 Datasheet - Page 10

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HYS64V2100GCU-10

Manufacturer Part Number
HYS64V2100GCU-10
Description
3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
A serial presence detect storage device - E
about the module configuration, speed, etc. is written into the E
production using a serial presence detect protocol ( I
SPD-Table:
Semiconductor Group
Byte#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
0
1
2
3
4
5
6
7
8
9
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x 8
SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (cont’ d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-back ran-
dom column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
SDRAM Device Attributes :General
SDRAM Cycle Time at CL = 2
SDRAM Access time from Clock at CL = 2
SDRAM Cycle Time at CL = 1
SDRAM Access time from Clock at CL=1
Minimum Row Precharge Time
Description
2
PROM - is assembled onto the module. Information
10
2
C synchronous 2-wire bus)
1, 2, 4, 8 & full page
8.0 / 10.0 / 12.0 ns
CAS latency = 1, 2
SPD Entry Value
non buffered/non
Write latency = 0
Vcc tol +/- 10%
CS latency = 0
Self-Refresh,
t
none / ECC
ccd
SDRAM
n/a / x8
15.0 ns
64 / 72
LVTTL
15.6 s
8.0 ns
9.0 ns
30 ns
30 ns
27 ns
2M x 64/72 SDRAM-Module
= 1 CLK
& 3
128
reg.
256
11
x8
HYS64(72)V2100G(C)U-10
2
9
1
0
2
PROM device during module
x64
A0
0B
6C
1E
04
01
01
80
8F
01
06
F0
90
78
80
08
09
40
00
00
80
08
00
01
02
07
01
00
Hex
x72
A0
6C
1E
80
04
0B
09
01
48
00
01
80
02
80
01
8F
02
07
01
00
06
F0
90
78
08
08
08
01

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