HYS64V2100GCU-10 SIEMENS [Siemens Semiconductor Group], HYS64V2100GCU-10 Datasheet - Page 9

• Manufacturer Part Number: HYS64V2100GCU-10
• Description: 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Notes:
1. The specified values are valid when addresses are changed no more than once during tck(min.)
2. The specified values are valid when data inputs (DQ’ s) are stable during tRC(min.).
3. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must
4. AC timing tests have V
5. If clock rising time is longer than 1ns, a time (t
6. If t
7. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
8. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
9. Referenced to the time which the output achieves the open circuit condition, not to output voltage
10.t
Semiconductor Group
and when No Operation commands are registered on every rising clock edge during tRC(min).
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
point. The transition time is measured between V
with the AC output load circuit shown.
commands must be given to “ w ake-up“ the device.
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
levels.
DAL
T
is longer than 1 ns, a time (t
OUTPUT
is equivalent to t
CLOCK
INPUT
tSETUP
tHOLD
tLZ
DPL
il
= 0.4 V and V
tAC
+ t
1.4V
RP
tCL
.
T
-1) ns has to be added to this parameter.
tCH
tOH
ih
= 2.4 V with the timing referenced to the 1.4 V crossover
tAC
t
tHZ
T
2.4 V
0.4 V
9
T
/2 -0.5) ns has to be added to this parameter.
ih
and V
1.4V
il
. All AC measurements assume t
2M x 64/72 SDRAM-Module
fig.1
HYS64(72)V2100G(C)U-10
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
50 pF
T
=1ns