HY5DU283222AF-5 HYNIX [Hynix Semiconductor], HY5DU283222AF-5 Datasheet - Page 29

• Manufacturer Part Number: HY5DU283222AF-5
• Description: 128M(4Mx32) GDDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

5.
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tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
Signal transitions through the DC region must be monotonic.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.