HY5PS1G831LF-C4 HYNIX [Hynix Semiconductor], HY5PS1G831LF-C4 Datasheet
HY5PS1G831LF-C4
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HY5PS1G831LF-C4 Summary of contents
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DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Dec 2006 HY5PS1G431(L)F ...
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Revision History Rev. 0.1 Preliminary Corrected typos of Pin description & tRFC spec. , 0.2 Added IDD spec. Editorial Clean up, Transfered Functional description, command truth table pages and Some contents of Operating conditions to <Device Operation & timing diagram> ...
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Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & ...
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Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD=1.8V • VDDQ=1.8V +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface ...
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Pin Configuration & Address Table 256Mx4 DDR2 Pin Configuration 1 NC VDD NC VSSQ VDDQ DQ1 NC VSSQ VDDL VREF CKE BA2 BA0 A10 VSS VDD A12 NC Bank Address Auto Precharge Flag Row Address Column Address Rev. 1.2 ...
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DDR2 PIN CONFIGURATION 1 NC VDD NU/RDQS DQ6 VSSQ VDDQ DQ1 DQ4 VSSQ VDDL VREF CKE BA2 BA0 A10 VSS A3 A7 VDD A12 NC NC ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address ...
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PIN DESCRIPTION PIN TYPE CK, CK Input CKE Input CS Input Input ODT RAS, CAS, WE Input DM Input (LDM, UDM) BA0 - BA2 Input A0 -A15 Input DQ Input/Output Rev. 1.2 / Dec 2006 Clock: CK and CK ...
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PIN TYPE DQS, (DQS) (UDQS),(UDQS) Input/Output (LDQS),(LDQS) (RDQS),(RDQS Supply DDQ VSSQ Supply V Supply DDL V Supply SSDL VDD Supply V Supply SS V Supply REF Rev. 1.2 / Dec 2006 Data Strobe : Output with read data, ...
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Maximum DC Ratings 2.1 Absolute Maximum DC Ratings Symbol Parameter VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss V V Voltage on any ...
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AC & DC Operating Conditons 3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions (SSTL_1.8) Symbol Parameter VDD Supply Voltage VDDL Supply Voltage for DLL VDDQ Supply Voltage for Output VREF Input Reference Voltage VTT Termination Voltage There is ...
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DC & AC Logic Input Levels 3.2.1 Input DC Logic Leve Symbol Parameter V (dc) dc input logic high IH V (dc) dc input logic low IL 3.2.2 Input AC Logic Level Symbol Parameter V (ac) ac input logic ...
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Differential Input AC logic Level Symbol Parameter V (ac) ac differential input voltage ID V (ac) ac differential cross point voltage specifies the allowable DC execution of each input of differential pair such as CK, CK, ...
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Output Buffer Characteristics 3.3.1 Output AC Test Conditions Symbol V Output Timing Measurement Reference Level OTR 1. The VDDQ of the device under test is referenced. 3.3.2 Output DC Current Drive Symbol I Output Minimum Source DC Current OH(dc) ...
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Note 5: The absolute value of the slew rate as measured from equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. Note 6: This ...
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IDD Specifications & Test Conditions IDD Specifications(max) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5 Normal IDD6 Low power IDD7 Rev. 1.2 / Dec 2006 DDR2 400 x4/x8 100 110 ...
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IDD Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1-5) Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RAS min(IDD) ; IDD0 ...
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For purposes of IDD testing, the following parameters are to be utilized Parameter CL(IDD) t RCD(IDD) t RC(IDD) t RRD(IDD)-x4/x8 t RRD(IDD)-x16 t CK(IDD) t RASmin(IDD) t RASmax(IDD) t RP(IDD) t RFC(IDD)-256Mb t RFC(IDD)-512Mb t RFC(IDD)-1Gb t RFC(IDD)-2Gb Detailed IDD7 ...
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Input/Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, ...
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Timing Parameters by Speed Grade Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time DQ and DM ...
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Parameter Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to ...
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Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time DQ and DM input hold time Control & ...
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Parameter Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to ...
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General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For ...
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VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via ...
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Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used ...
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These values are typically not subject to production test. They are verified by design and characterization. Fig. a Illustration of nominal slew rate for tIS,tDS CK,DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF V ...
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Fig. -b Illustration of tangent line for tIS,tDS CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF V (dc)max IL V (ac)max IL Nomial line Vss Delta TF Setup Slew Rate Tangent line[V = ...
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Fig. -c Illustration of nominal line for tIH, tDH CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min REF region V (dc) REF V (dc)max IL V (ac)max IL Vss Hold Slew Rate V ...
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Fig. -d Illustration of tangent line for tIH , tDH CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF REF region V (dc)max IL V (ac)max IL Vss Hold Slew Rate ...
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Command / 0.8 -25 Address Slew 0.7 -43 rate(V/ns) 0.6 -67 0.5 -100 ...
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These values are typically not subject to production test. They are verified by design and characterization. 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but ...
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The actual voltage measurement points are not critical as long as ...
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Package Dimensions Package Dimension(x4,x8) 68Ball Fine Pitch Ball Grid Array Outline 11.9 +/- 0.10 A1 Ball Mark < Top View> A1 Ball Mark 0.80 0. 6.40 < Bottom View> Rev. 1.2 / Dec ...