HY5PS1G831LF-C4 HYNIX [Hynix Semiconductor], HY5PS1G831LF-C4 Datasheet - Page 24

• Manufacturer Part Number: HY5PS1G831LF-C4
• Description: 1Gb DDR2 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.2 / Dec 2006
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and
its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.
Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must
be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
may be guaranteed by device design or tester correlation.
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
t
RPRE
DQS
DQS
WPRE
Figure -- Data output (read) timing
V
V
IL
IH
(ac)
(ac)
t
DMin
DS
t
t
CL
DQSQmax
D
Figure -- Data input (write) timing
t
DQSH
V
V
IH
IL
(ac)
(ac)
t
DMin
t
DS
QH
D
Q
t
DQSL
DMin
Q
D
t
DH
V
IH
V
IL
(dc)
(dc)
t
DQSQmax
DMin
Q
V
D
t
IL
DH
(dc)
V
IH
t
WPST
(dc)
1HY5PS1G431(L)F
1HY5PS1G831(L)F
t
t
RPST
QH
Q
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