HY5PS1G831LF-C4 HYNIX [Hynix Semiconductor], HY5PS1G831LF-C4 Datasheet - Page 14

Manufacturer Part Number

HY5PS1G831LF-C4

Description

1Gb DDR2 SDRAM

Manufacturer

HYNIX [Hynix Semiconductor]

Datasheet

1.HY5PS1G831LF-C4.pdf (33 pages)

Rev. 1.2 / Dec 2006

Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as

measured from AC to AC. This is guaranteed by design and characterization.

Note 6: This represents the step size when the OCD is near 18 ohms at nominal conditions across all process cor-

ners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the

OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.

Output Slew rate load:

Note 7: DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.

Note 8: Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in

tDQSQ and tQHS specification.

Output

(Vout)

VTT

25 ohms

Reference

point

1HY5PS1G431(L)F

1HY5PS1G831(L)F