H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 255

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 11.5.
11.5
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.
Table 11.2 WDT Interrupt Source
Name
WOVI
Overflow signal
(internal signal)
φ
OVF
RESO signal
Internal reset
signal
TCNT
RESO Signal Output Timing
RESO
Interrupt Sources
RESO
RESO
Interrupt Source
TCNT overflow
Figure 11.5 Output Timing of RESO
H'FF
Interrupt Flag
OVF
Rev. 2.00 Mar 21, 2006 page 217 of 518
RESO signal
RESO
RESO
132 states
Section 11 Watchdog Timer (WDT)
518 states
H'00
REJ09B0299-0200