H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 430

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface LPC Interface (LPC)
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3.
Rev. 2.00 Mar 21, 2006 page 392 of 518
REJ09B0299-0200
LCLK
LFRAME
LAD3–LAD0
Number of clocks
LCLK
LFRAME
LAD3–LAD0
1
Start
Start
Cycle type,
direction,
and size
Cycle type,
direction,
and size
Figure 15.2 Typical LFRAME
1
Figure 15.3 Abort Mechanism
ADDR
ADDR
4
TAR
TAR
Too many Syncs
cause timeout
LFRAME
LFRAME
LFRAME Timing
2
Sync
Sync
1
Slave must stop driving
Data
2
TAR
2
Start
Master will
drive high
1