MAX11329ATJ+ Maxim Integrated, MAX11329ATJ+ Datasheet - Page 17

• Manufacturer Part Number: MAX11329ATJ+
• Description: Analog to Digital Converters - ADC 10Bit 16Ch 3Mbps Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11329ATJ+

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 72.3 dB
• Interface Type: BiCMOS
• Operating Supply Voltage: 1.5 V to 3.6 V, 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-32
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

Figure 4. Unipolar Transfer Function for 12-Bit Resolution
result contains 2 bytes, with the MSB preceded by four
leading channel address bits. After each falling edge of
CS, the oldest available byte of data is available at DOUT.
When the FIFO is empty, DOUT is zero.
Apply a soft reset when changing from internal to external
clock mode: RESET [1:0] = 10. The detailed operation
of external clock mode is dependent on the mode of
operation selected for the device using SCAN[3:0] bit
settings (see
inputs are sampled at the falling edge of CS. Serial clock
(SCLK) is used to perform the conversion.
Depending on the mode selected, the sequencer reads
in the channel to be converted from the serial data input
(DIN) at each frame (e.g. manual mode). The conversion
results are sent to the serial output (DOUT) at the next
frame.
In other external clocked modes the sequence of channel
to be converted is determined by the mode (SCAN[3:0])
selected in
more detail on programming modes.
Maxim Integrated
OUTPUT CODE (hex)
FFD
FFC
FFB
FFF
FFE
004
003
002
001
000
0
Table
Post-Mux External Signal Conditioning Access
Table
1
FS = V
ZS = 0
1 LSB =
2
3. See the
REF+
3). In external clock mode the analog
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
V
4096
3
REF+
INPUT VOLTAGE (LSB)
4
Applications Information
FS -1.5 LSB
External Clock
FS
for
Figure 5. Bipolar Transfer Function for 12-Bit Resolution
Apply a soft reset when changing from internal to exter-
nal clock mode: RESET [1:0] = 10. The MAX11329–
MAX11332 operate from an internal oscillator, which
is accurate within Q15% of the 40MHz nominal clock
rate. Request internally timed conversions by writing the
appropriate sequence to the ADC Mode Control register
(Table
The wake-up, acquisition, conversion, and shutdown
sequences are initiated through CNVST and are per-
formed automatically using the internal oscillator. Results
are added to the internal FIFO.
With CS high, initiate a scan by setting CNVST low for
at least 5ns before pulling it high
MAX11329–MAX11332 wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes
low before pulling CS low to communicate with the serial
interface. EOC stays low until CS or CNVST is pulled low
again. Do not initiate a second CNVST before EOC goes
low; otherwise, the FIFO may become corrupted.
OUTPUT CODE (hex)
MAX11329–MAX11332
7FF
7FE
001
000
FFF
FFE
801
800
2).
-FS
+FS =
ZS = 0
-FS =
1 LSB =
-FS +0.5 LSB
V
-V
REF+
2
2
V
REF+
4096
REF+
INPUT VOLTAGE (LSB)
0
+FS -1.5 LSB
(Figure
Internal Clock
6). Then, the
+FS
17