MAX11329ATJ+ Maxim Integrated, MAX11329ATJ+ Datasheet - Page 31

• Manufacturer Part Number: MAX11329ATJ+
• Description: Analog to Digital Converters - ADC 10Bit 16Ch 3Mbps Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11329ATJ+

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 72.3 dB
• Interface Type: BiCMOS
• Operating Supply Voltage: 1.5 V to 3.6 V, 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-32
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

Figure 10. SampleSet Timing Diagram
1) Configure the ADC (set the MSB on DIN to 1).
2) Program ADC mode control (set the MSB on DIN to 0)
See
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
Maxim Integrated
to begin the conversion process or to control power
management features.
• If ADC mode control is written during a conversion
• If configuration data (MSB on DIN is a 1) is written
DOUT
SCLK
Figure 11
DIN
CS
sequence, the ADC finishes the present conver-
sion and at the next falling edge of CS initiates its
new instruction.
during a conversion sequence, the ADC finishes
the present conversion in the existing scan mode.
However, data on DOUT is not valid in following
frames until a new ADC mode control instruction
is coded.
Programming Sequence Flow Chart
1
Post-Mux External Signal Conditioning Access
Layout, Grounding, and Bypassing
for programming sequence.
Applications Information
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
WRITE SampleSet REGISTER
DEFINE SEQ_LENGTH
How to Program Modes
16
DD
1
,
ENTRY 1
RISING EDGE DEPENDS IN SEQ_LENGTH
OVDD, and REF affects the ADC’s perfor mance. Bypass
the V
bypass capacitors. Minimize capacitor lead and trace
lengths for best supply-noise rejection.
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is the
interval between the application of an input voltage step
and the point at which the output signal reaches and
stays within a given error band centered on the result-
ing steady-state amplifier output level. The ADC input
sampling capacitor charges during the sampling cycle,
referred to as the acquisition period. During this acquisi-
tion period, the settling time is affected by the input resis-
tance and the input sampling capacitance. This error
can be estimated by looking at the settling of an RC time
constant using the input capacitance and the source
impedance over the acquisition time period.
shows a typical application circuit. The MAX4430, offer-
ing a settling time of 37ns at 16-bit resolution, is an excel-
lent choice for this application.
Table 15
fiers for MAX11129–MAX11132.
TIME BETWEEN CS FALLING AND
ENTRY 2
LOAD SampleSet PATTERN
DD
MAX11329–MAX11332
, OVDD, and REF to ground with 0.1FF and 10FF
lists serveral recommended operational ampli-
ENTRY N = (SEQ_LENGTH)
Choosing an Input Amplifier
OR CONTINUE WITH ADDITIONAL
WRITE ADC MODE CONTROL
CONFIGURATION SETTINGS
1
Figure 13
31