MAX11329ATJ+ Maxim Integrated, MAX11329ATJ+ Datasheet - Page 21

• Manufacturer Part Number: MAX11329ATJ+
• Description: Analog to Digital Converters - ADC 10Bit 16Ch 3Mbps Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11329ATJ+

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 72.3 dB
• Interface Type: BiCMOS
• Operating Supply Voltage: 1.5 V to 3.6 V, 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-32
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

up to 16-channel conversions in ascending order. In this
case, the effective throughput per channel is 3Msps/16
channel or 187.5ksps. The maximum input frequency
that the ADC can resolve (Nyquist Theorem) is 93.75kHz.
If all 16 channels must be measured, with some chan-
nels having greater than 93.75kHz input frequency, the
user must revert back to manual mode requiring con-
stant communication on the serial interface. SampleSet
technology solves this problem.
SampleSet use-model example.
In averaging mode, the device performs the specified
number of conversions and returns the average for each
requested result in the FIFO. The averaging mode works
with internal clock only.
Table 1. Register Access and Control
Table 2. ADC Mode Control Register
Maxim Integrated
ADC Mode Control
ADC Configuration
Unipolar
Bipolar
RANGE
Custom Scan0
Custom Scan1
SampleSet
Reserved. Do not use.
CHSEL[3:0]
REG_CNTL
RESET[1:0]
BIT NAME
SCAN[3:0]
REGISTER NAME
Post-Mux External Signal Conditioning Access
14:11
10:7
BIT
6:5
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
15
DEFAULT
STATE
0001
0000
00
0
Figure 9
BIT 15
Averaging Mode
0
1
1
1
1
1
1
1
1
Set to 0 to select the ADC Mode Control register
ADC Scan Control register (Table 3)
Analog Input Channel Select register (Table 4).
See Table 3 to determine which modes use CHSEL[3:0] for the channel scan
instruction.
RESET1
provides a
0
0
1
1
REGISTER IDENTIFICATION CODE
BIT 14
DIN
0
0
0
0
0
0
0
1
RESET0
BIT 13
0
1
0
1
DIN
When the Unipolar or Bipolar registers are configured
as pseudo-differential or fully differential, the analog
input pairs are repeated in this automated mode. For
example, if N is set to 15 to scan all 16 channels and
all analog input pairs are configured for fully-differential
conversion, the ADC converts the channels twice. In this
case, the user may avoid dual conversions on input pairs
by implementing Manual mode or using Custom_Int or
Custom_Ext scan modes and only scan even (or odd)
channels (e.g. 0, 2, 4).
0
0
0
0
1
1
1
1
MAX11329–MAX11332
No reset
Reset the FIFO only (resets to zero)
Reset all registers to default settings (includes FIFO)
Unused
BIT 12
DIN
FUNCTION
0
0
1
1
0
0
1
1
Scan Modes and Unipolar/Bipolar Setting
BIT 11
DIN
0
1
0
1
0
1
0
1
FUNCTION
DIN ≡ DATA INPUTS
BIT [10:0]
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
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