MAX11329ATJ+ Maxim Integrated, MAX11329ATJ+ Datasheet - Page 3

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MAX11329ATJ+

Manufacturer Part Number
MAX11329ATJ+
Description
Analog to Digital Converters - ADC 10Bit 16Ch 3Mbps Precision ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX11329ATJ+

Rohs
yes
Number Of Channels
16/8
Architecture
SAR
Conversion Rate
3 MSPs
Resolution
10 bit
Input Type
Single-Ended/Pseudo-Differential
Snr
72.3 dB
Interface Type
BiCMOS
Operating Supply Voltage
1.5 V to 3.6 V, 2.35 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TQFN-EP-32
Maximum Power Dissipation
2758 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
External
ELECTRICAL CHARACTERISTICS (MAX11331/MAX11332) (continued)
(V
unless otherwise noted. Typical values are at T
Maxim Integrated
Crosstalk
CONVERSION RATE
Power-Up Time
Acquisition Time
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Absolute Input Voltage Range
Static Input Leakage Current
Input Capacitance
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
REF+ Input Current
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
Input Voltage Low
Input Voltage High
Input Hysteresis
DD
= 2.35V to 3.6V, V
PARAMETER
Post-Mux External Signal Conditioning Access
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
OVDD
= 1.5V to 3.6V, f
SYMBOL
t
V
V
f
V
I
t
CONV
C
V
SCLK
REF+
ACQ
I
REF+
HYST
t
V
REF-
V
ILA
PU
INA
AIN
SAMPLE
IH
IL
A
= +25NC.) (Note 2)
-0.5dB below full-scale of 99.2432kHz
sine wave input to the channel being
sampled, apply full-scale 69.2139kHz
sine wave signal to all 15 nonselected
input channels.
Conversion cycle, external clock
Internally clocked (Note 8)
Externally clocked, f
16 cycles (Note 8)
RMS
Unipolar, (single ended and pseudo-
differential)
Bipolar
(Note 9)
AIN+, AIN- relative to GND
V
During acquisition time;
RANGE bit = 0 (Note 10)
During acquisition time;
RANGE bit = 1 (Note 10)
V
V
= 3Msps, f
AIN
REF+
REF+
= V
= 2.5V, f
= 2.5V, f
DD
SCLK
, GND
CONDITIONS
SAMPLE
SAMPLE
= 48MHz, 50% duty cycle, V
Range bit set to 0
Range bit set to 1
SCLK
MAX11329–MAX11332
= 3Msps
= 0Msps
= 48MHz,
-V
-V
V
O 0.75
0.48
OVDD
MIN
333
-0.1
-0.3
REF+
REF+
REF+
0
1
/2
= V
V
O 0.15
-0.01
TYP
OVDD
110
-88
DD
2.1
7.5
0.1
52
30
15
8
V
V
, T
DD
REF+
A
V
+ 50mV
= -40NC to +125NC,
V
V
V
REF+
O 0.25
MAX
Q1.5
OVDD
REF+
REF+
48
+ 0.1
+1
2
/2
UNITS
Cycles
MHz
mV
dB
FA
pF
FA
ns
µs
ns
ns
ps
V
V
V
V
V
V
3

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