S9S12G128F0VLF Freescale Semiconductor, S9S12G128F0VLF Datasheet - Page 317

• Manufacturer Part Number: S9S12G128F0VLF
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Read: Anytime
Write: Never
8.3.2.3
Freescale Semiconductor
Address: 0x0021
Address: 0x0022
SSF[2:0]
Reset
Reset
Field
POR
TBF
2–0
7
W
W
R
R
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGCNT[7]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
TBF
—
Debug Trace Control Register (DBGTCR)
0
0
0
7
7
TSOURCE
Table 8-6. SSF[2:0] — State Sequence Flag Bit Encoding
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 8-5. Debug Trace Control Register (DBGTCR)
101,110,111
Figure 8-4. Debug Status Register (DBGSR)
SSF[2:0]
MC9S12G Family Reference Manual, Rev.1.23
000
001
010
011
100
Table 8-5. DBGSR Field Descriptions
0
0
0
0
0
5
5
0
0
0
0
0
4
4
Description
State0 (disarmed)
Current State
Final State
Reserved
0
0
0
State1
State2
State3
0
3
3
TRCMOD
SSF2
Table 8-6
0
0
0
2
2
S12S Debug Module (S12SDBGV2)
.
SSF1
0
0
0
0
1
1
TALIGN
SSF0
0
0
0
0
0
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