S9S12G128F0VLF Freescale Semiconductor, S9S12G128F0VLF Datasheet - Page 651

• Manufacturer Part Number: S9S12G128F0VLF
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
See
To calculate the output duty cycle (high time as a% of period) for a particular channel:
For boundary case programming values, please refer to
1
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x001C = PWMDTY0, 0x001D = PWMDTY1, 0x001E = PWMDTY2, 0x001F = PWMDTY3
Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Reset
•
•
•
Section 19.4.2.3, “PWM Period and Duty”
W
R
The channel is disabled
Polarity = 0 (PPOL x =0)
Polarity = 1 (PPOLx = 1)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Bit 7
1
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is one, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is zero, the output starts
low and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
Figure 19-14. PWM Channel Duty Registers (PWMDTYx)
1
6
6
MC9S12G Family Reference Manual, Rev.1.23
1
5
5
for more information.
NOTE
NOTE
1
4
4
Section 19.4.2.8, “PWM Boundary
1
3
3
Pulse-Width Modulator (S12PWM8B8CV2)
1
2
2
1
1
1
Cases”.
Bit 0
1
0
653