S9S12GN32F0VLF Freescale Semiconductor, S9S12GN32F0VLF Datasheet - Page 253

• Manufacturer Part Number: S9S12GN32F0VLF
• Description: 16-bit Microcontrollers - MCU 16-bit32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2048 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

the ETRIG will be driven by the PWM internally. If the related PWM channel is not enabled, the ETRIG
function will be triggered by other functions on the pin including general-purpose input.
Table 2-94
TSSOP with shared ACMP analog input functions on port AD pins only.
2.6.5
The
development and debugging without need to have the actual target package at hand. Cross-device
programming for the shared functions is also supported because smaller package sizes than the given
device is offered in can be selected
The PKGCR can be written in normal mode once after reset to overwrite the factory pre-programmed
value, which determines the actual package. Further attempts are blocked to avoid inadvertent changes
(blocking released in special mode). Trying to select a package larger than the given device is offered in
will be ignored and result in the “illegal” code being written.
When a smaller package is selected the pin availability and pin functionality changes according to the
target package specification. The input buffers of unused pins are disabled however the output functions
of unused pins are not disabled. Therefore these pins should be don’t-cared.
Depending on the different feature sets of the G-family derivatives the input buffers of specific pins, which
are shared with analog functions need to be explicitly enabled before they can be used with digital input
functions. For example devices featuring an ACMP module contain a control register for the related input
buffers, which is not available on other family members. Also larger devices in general feature more ADC
channels with individual input buffer enable bits, which are not present on smaller ones. These differences
need to be accounted for when developing cross-functional code.
1. Except G(A)128/G(A)96 in 20 TSSOP: Internal routing of PWM to ETRIG is not available.
Freescale Semiconductor
Package Code Register (PKGCR)
1
2
illustrates the resulting trigger sources and their dependencies. Shaded fields apply to 20
Emulation of Smaller Packages
Buffer Enable
Refer to
With higher priority than PWM on pin including ACMP enable (ACMPC[ACE]=1)
Port AD Input
0
0
0
0
1
1
1
1
NOTE/2-180
1
Enable
for enable condition
PWM
MC9S12G Family Reference Manual, Rev.1.23
0
0
1
1
0
0
1
1
1
.
allows the emulation of smaller packages to support software
Table 2-94. ETRIG Sources
Peripheral
Enable
0
1
0
1
0
1
0
1
2
Const. 1
Const. 1
Source
ETRIG
PWM
PWM
PWM
Pin
Pin
Pin
Forced High
Forced High
Internal Link
Internal Link
Driven by General-Purpose Function
Driven by Peripheral
Driven by PWM
Internal Link
Comment
Port Integration Module (S12GPIMV1)
255