S9S12GN32F0VLF Freescale Semiconductor, S9S12GN32F0VLF Datasheet - Page 688

no-image

S9S12GN32F0VLF

Manufacturer Part Number
S9S12GN32F0VLF
Description
16-bit Microcontrollers - MCU 16-bit32k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12GN32F0VLF

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
32 KB
Data Ram Size
2048 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12GN32F0VLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S12GN32F0VLFR
Manufacturer:
FREESCALE
Quantity:
20 000
Serial Communication Interface (S12SCIV5)
20.4.5.5
This module allows to check for collisions on the LIN bus.
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the
transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run
when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received
data is detected the following happens:
If the bit error detect feature is disabled, the bit error interrupt flag is cleared.
690
Output Transmit
Input Receive
Bit Error
Shift Register
Shift Register
The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
The transmission is aborted and the byte in transmit buffer is discarded.
the transmit data register empty and the transmission complete flag will be set
The bit error interrupt flag, BERRIF, will be set.
No further transmissions will take place until the BERRIF is cleared.
LIN Transmit Collision Detection
The RXPOL and TXPOL bit should be set the same when transmission
collision detect feature is enabled, otherwise the bit error interrupt flag may
be set incorrectly.
Receive Shift
Register
Transmit Shift
Register
Compare
Sample
Point
0
1
2
Figure 20-19. Timing Diagram Bit Error Detection
3
Synchronizer Stage
MC9S12G Family Reference Manual,
Figure 20-18. Collision Detect Principle
4
BERRM[1:0] = 0:1
5
Bus Clock
6
7
Compare Sample Points
NOTE
8
9
RXD Pin
TXD Pin
10
11
BERRM[1:0] = 1:1
12
Rev.1.23
13
14
LIN Physical Interface
15
0
Freescale Semiconductor
LIN Bus

Related parts for S9S12GN32F0VLF