S9S12GN16F0MLF Freescale Semiconductor, S9S12GN16F0MLF Datasheet - Page 392

Manufacturer Part Number

S9S12GN16F0MLF

16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Operating Supply Voltage

3.13 V to 5.5 V

Operating Temperature Range

- 40 C to + 85 C

Package / Case

Mounting Style

S12 Clock, Reset and Power Management Unit (S12CPMU)

10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register

The CPMUAPIRH and CPMUAPIRL registers allow the conﬁguration of the autonomous periodical

interrupt rate

Read: Anytime

Write: Anytime if APIFE=0. Else writes have no effect.

The period can be calculated as follows depending on logical value of the APICLK bit:

APICLK=0: Period = 2*(APIR[15:0] + 1) * f

APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period

Figure 10-20. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)

Autonomous Periodical Interrupt Rate Bits — These bits deﬁne the time-out period of the API. See

Figure 10-21. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)

(CPMUAPIRH / CPMUAPIRL)

For APICLK bit clear the ﬁrst time-out period of the API will show a latency

time between two to three f

release when the API feature gets enabled (APIFE bit set)

= Unimplemented or Reserved

for details of the effect of the autonomous periodical interrupt rate bits.

Table 10-19. CPMUAPIRH / CPMUAPIRL Field Descriptions

MC9S12G Family Reference Manual,

cycles due to synchronous clock gate

Freescale Semiconductor