S9S12G192F0VLH Freescale Semiconductor, S9S12G192F0VLH Datasheet
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S9S12G192F0VLH Summary of contents
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MC9S12G Family Reference Manual and Data Sheet S12 Microcontrollers MC9S12GRMV1 Rev.1.23 February 1, 2013 freescale.com ...
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... To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: freescale.com/ A full list of family members and options is included in the appendices. Freescale Semiconductor MC9S12G Family Reference Manual, Rev.1.23 2 ...
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... Added KGD information) • Added (Reason: Added KGD information) • Updated (Reason: Removed KGD information) Feb, 2012 1.23 • Added (Reason: Updated KGD information) Freescale Semiconductor Description Appendix A, “Electrical Characteristics” Appendix A, “Electrical Characteristics” Chapter 1, “Device Overview MC9S12G-Family” Appendix A, “Electrical Characteristics” ...
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... This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual 4 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1 .931 Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1 .983 Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1 .1035 Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1 .1087 Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1 .1139 Freescale Semiconductor MC9S12G Family Reference Manual, Rev.1.23 15 ...
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... Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1191 Appendix B Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1249 Appendix C Ordering and Shipping Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .1269 Appendix D Package and Die Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1271 16 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.8 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.8.1 S12GN16 and S12GN32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.8.2 S12GNA16 and S12GNA32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.8.3 S12GN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.8.4 S12G48 and S12G64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.8.5 S12GA48 and S12GA64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.8.6 S12G96 and S12G128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 1.8.7 S12GA96 and S12GA128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 1.8.8 S12G192 and S12G240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 1.8.9 S12GA192 and S12GA240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Freescale Semiconductor Chapter 1 MC9S12G Family Reference Manual, Rev.1.23 19 ...
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... Pins PT7 173 2.3.8 Pins PS7 175 2.3.9 Pins PM3 177 2.3.10 Pins PP7 177 2.3.11 Pins PJ7 179 2.3.12 Pins AD15 180 2.4 PIM Ports - Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 2.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 2.4.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 2.4.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 20 Chapter 2 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 4.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 4.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 4.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 S12G Memory Map Controller (S12GMMCV1) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 5.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 5.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 5.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 5.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Freescale Semiconductor Chapter 3 Chapter 4 Chapter 5 MC9S12G Family Reference Manual, Rev.1.23 21 ...
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... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 7.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 7.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 22 Chapter 6 Interrupt Module (S12SINTV1) Chapter 7 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 8.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 8.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 8.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 8.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 8.5.2 Scenario 348 8.5.3 Scenario 349 8.5.4 Scenario 349 8.5.5 Scenario 349 8.5.6 Scenario 351 8.5.7 Scenario 351 8.5.8 Scenario 351 8.5.9 Scenario 352 8.5.10 Scenario 352 8.5.11 Scenario 352 Freescale Semiconductor Chapter 8 MC9S12G Family Reference Manual, Rev.1.23 23 ...
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... External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 10.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 10.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 10.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 10.5.3 Power-On Reset (POR 414 10.5.4 Low-Voltage Reset (LVR 414 10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 10.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 24 Chapter 9 Security (S12XS9SECV2) Chapter 10 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 12.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 12.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 Analog-to-Digital Converter (ADC10B12CV2) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Freescale Semiconductor Chapter 11 Chapter 12 Chapter 13 MC9S12G Family Reference Manual, Rev.1.23 25 ...
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... Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 15.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 15.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 15.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 26 Chapter 14 Chapter 15 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Mode “Unbuffered DAC” 580 17.5.5 Mode “Unbuffered DAC with Operational Amplifier” 580 17.5.6 Mode “Buffered DAC” 580 17.5.7 Analog output voltage calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Freescale Semiconductor Chapter 16 Chapter 17 Chapter 18 MC9S12G Family Reference Manual, Rev.1.23 27 ...
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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 19.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 19.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 19.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 Serial Communication Interface (S12SCIV5) 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 28 Chapter 19 Chapter 20 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 21.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 21.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 21.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 21.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Freescale Semiconductor Chapter 21 MC9S12G Family Reference Manual, Rev.1.23 29 ...
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... Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 23.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 23.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 23.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 23.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 23.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 23.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 30 Chapter 22 Timer Module (TIM16B6CV3) Chapter 23 Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... KByte Flash Module (S12FTMRG32K1V1) 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 25.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 25.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 25.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 25.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 25.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 Freescale Semiconductor Chapter 24 Chapter 25 MC9S12G Family Reference Manual, Rev.1.23 31 ...
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... Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 26.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 929 26.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 930 26.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 64 KByte Flash Module (S12FTMRG64K1V1) 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 32 Chapter 26 Chapter 27 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 28.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1015 28.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 28.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 28.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 28.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 28.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 28.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 Freescale Semiconductor Chapter 28 MC9S12G Family Reference Manual, Rev.1.23 33 ...
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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 30.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 30.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091 30.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091 30.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095 30.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113 30.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113 30.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113 30.4.3 Internal NVM resource (NVMRES 1114 34 Chapter 29 Chapter 30 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1188 31.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1188 31.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188 A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 Freescale Semiconductor Chapter 31 Appendix A Electrical Characteristics MC9S12G Family Reference Manual, Rev.1.23 35 ...
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... A.16 ADC Conversion Result Reference 1247 B.1 Detailed Register Map 1249 Ordering and Shipping Information C.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269 D.1 100 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272 D.2 64 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 36 Appendix B Detailed Register Address Map Appendix C Appendix D Package and Die Information MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
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... D.3 48 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 D.4 48 QFN Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 D.5 32 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 D.6 20 TSSOP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 D.7 KGD Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 Freescale Semiconductor MC9S12G Family Reference Manual, Rev.1.23 37 ...
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... MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 37
... The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602 Freescale Semiconductor Description of Changes Section 1.14, “Autonomous Clock (ACLK) Figure 1-15 ...
Page 38
... Rev.1.23 Freescale Semiconductor 240 240 — ...
Page 39
... Table 1-2. Maximum Peripheral Availability per Package Peripheral 20 TSSOP MSCAN — SCI0 Yes SCI1 — SCI2 — SPI0 Yes SPI1 — SPI2 — Timer Channels … 3 Freescale Semiconductor Table 1-1. MC9S12G-Family Overview 8 — — 12 — — — — — — — — — — — — — ...
Page 40
... Yes — Yes Yes Yes 26 40 MC9S12G Family Reference Manual, 64 LQFP 100 LQFP KGD (Die … … … … … 15 Yes Yes Yes Yes Yes — Rev.1.23 Freescale Semiconductor … 7 Yes Yes — 86 ...
Page 41
... Control registers to enable/disable pull devices and select pullups/pulldowns on ports and AD on per-pin basis • Single control register to enable/disable pull devices on ports and E, on per-port basis and on BKGD pin • Control registers to enable/disable open-drain (wired-or) mode on ports S and M Freescale Semiconductor MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family 43 ...
Page 42
... Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – External 4–16 MHz resonator/crystal (XOSCLCP) – Internal 1 MHz RC oscillator (IRC) 44 Table A-4) Table A-4) MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 43
... Flexible identifier acceptance filter programmable as: — 32-bit — 16-bit — 8-bit • Wakeup with integrated low pass filter option • Loop back for self test • Listen-only mode to monitor CAN bus Freescale Semiconductor MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family 45 ...
Page 44
... Multiple channel scans — Precision fixed voltage reference for ADC conversions — • Pins can also be used as digital I/O including wakeup capability 1. 12-bit resolution only available on S12GA192 and S12GA240 devices analog-to-digital converter MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 45
... Two types of comparator matches — Tagged This matches just before a specific instruction begins execution — Force This is valid on the first instruction boundary after a match occurs • Four trace modes Freescale Semiconductor MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family 47 ...
Page 46
... LQFP, 0.8 mm pitch outline — 20 TSSOP, 0.65 mm pitch, 4 6.5 mm outline — Known good die (KGD), unpackaged 1.5 Block Diagram Figure 1-1 shows a block diagram of the MC9S12G-Family –40˚C to 125˚ 150˚C J MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 47
... Converter AMPP PD[7:0] Not all pins or all peripherals are available on all devices and packages. 1.6 Family Memory Map Table 1-3 shows the MC9S12G-Family register memory map. Address 0x0000–0x0009 Freescale Semiconductor ACMP Analog Comparator DAC0 Digital-Analog Converter Voltage Regulator TIM Input: 3.13V – 5.5V 16-bit 6 … 8 channel ...
Page 48
... PIM (Port Integration Module) Reserved CPMU (Clock and Power Management) Reserved 8 DAC0 (Digital to Analog Converter) MC9S12G Family Reference Manual, Size (Bytes 192 112 16 192 8 Rev.1.23 Freescale Semiconductor ...
Page 49
... PF_LOW_UNP 0xC000 0x8000 1 (unpaged) PPAGES 0x0F EEPROM 512 [Bytes] EEPROM_HI 0x05FF 0x07FF Freescale Semiconductor Module DAC1 (Digital to Analog Converter) Reserved NOTE Table 1-3 is not allocated to any module. shows the address ranges and mapping to 256K global memory S12G48 S12G64 S12GN48 32KB 48KB 64KB ...
Page 50
... MC9S12G Family Reference Manual, S12G192 S12G240 S12G128 S12GA192 S12GA240 8192 8192 11264 0x2000 0x1400 0x1400 0x1400- — 0x1FFF 4KB 3KB — Rev.1.23 Freescale Semiconductor 11264 — — ...
Page 51
... Page 0xD 0x8000 Paging Window Paging Window 0xC000 Flash Space Flash Space Page 0xF Page 0xF 0xFFFF Freescale Semiconductor Figure 1-2. MC9S12G Global Memory Map MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family Global Memory Map 0x0_0000 Register Space Register Space 0x0_0400 EEPROM ...
Page 52
... MC9S12G Family Reference Manual, Table 1-5 shows the assigned part ID Part ID 0xF080 0xF080 0xF080 0xF080 0xF180 0xF180 0xF180 0xF180 0xF280 1 0xF280 2 0xF281 0xF280 1 0xF280 2 0xF281 1 0xF280 2 0xF281 0xF380 3 0xF380 4 0xF381 0xF380 3 0xF380 4 0xF381 Rev.1.23 Freescale Semiconductor ...
Page 53
... MCU function causes a reset. The RESET pin has an internal pull-up device. 1.7.2.2 TEST — Test Pin This input only pin is reserved for factory test. This pin has an internal pull-down device. Freescale Semiconductor 48 LQFP 20 TSSOP 32 LQFP 48 QFN ...
Page 54
... Out of reset the pull-up devices are disabled. 1.7.2.10 PE[1:0] — Port E I/O Signals PE[1:0] are general-purpose input or output signals. The signals can have pull-down device, enabled by a single control bit for this signal group. Out of reset the pull-down devices are enabled. 56 NOTE MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 55
... ACMPP is the non-inverting input of the analog comparator. 1.7.2.17.2 ACMPM — Inverting Analog Comparator Input ACMPM is the inverting input of the analog comparator. 1.7.2.17.3 ACMPO — Analog Comparator Output ACMPO is the output of the analog comparator. Freescale Semiconductor MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family 57 ...
Page 56
... Those signals are associated with the MOSI functionality of the serial peripheral interfaces SPI2-0. They act as master output during master mode or as slave input during slave mode. 1.7.2.20 SCI Signals 1.7.2.20.1 RXD[2:0] Signals Those signals are associated with the receive functionality of the serial communication interfaces SCI2-0. 58 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 57
... API_EXTCLK This signal is associated with the output of the API clock (API_EXTCLK). 1.7.2.24 IOC[7:0] Signals The signals IOC[7:0] are associated with the input capture or output compare functionality of the timer (TIM) module. Freescale Semiconductor NOTE NOTE MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family 59 ...
Page 58
... VSS — Core Ground Pin The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current path is through the VSS pin. 60 NOTE NOTE 1.8 Device Pinouts for further details. NOTE 1.8 Device Pinouts for further details. MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 59
... For the 20- and 32-pin package the VDDX, VDDR and VDDA supplies are combined on one pin. VSSXA 0V Return ground for I/O driver and VDDA analog supply VRH 3.15V – 5.0 V Reference voltage for the analog-to-digital converter. Freescale Semiconductor NOTE Section 1.8, “Device Connection” Description MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family Pinouts” ...
Page 60
... V PERT/PPST DDX — — V PERT/PPST DDX — — V PER1AD/PPS1AD DDA — — V PER1AD/PPS1AD DDA — — V PER1AD/PPS1AD DDA Rev.1.23 Freescale Semiconductor Internal Pull Resistor Reset State Up Up PULLUP — — Down — Down Down Up Disabled Disabled Disabled Disabled Disabled ...
Page 61
... Func. 16 PAD3 KWAD3 17 PAD4 KWAD4 ETRIG2 18 PAD5 KWAD5 ETRIG3 19 PS4 ETRIG2 20 PS5 IOC2 1 The regular I/O characteristics (see Section A.2, “I/O Freescale Semiconductor Function 3rd 4th 5th 6th Func. Func Func Func AN3 ACMPO — — PWM2 IOC2 RXD0 PWM3 IOC3 TXD0 PWM2 ...
Page 62
... MC9S12G Family Reference Manual, PAD7/KWAD7/AN7/ACMPM PAD6/KWAD6/AN6/ACMPP PAD5/KWAD5/AN5/ACMPO PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 Internal Pull Resistor Power Supply 5th CTRL Func — V PULLUP DDX — — — — — — Rev.1.23 Freescale Semiconductor Reset State — — ...
Page 63
... PS0 RXD0 26 PS1 TXD0 27 PS4 PWM4 28 PS5 IOC4 29 PS6 IOC5 30 PS7 API_EXTCLK 31 PM0 — 32 PM1 — Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — — — — — — — — ETRIG0 ...
Page 64
... Figure 1-5. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32 66 Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled S12GN16 4 S12GN32 VSS 48-Pin LQFP/QFN MC9S12G Family Reference Manual, PAD7/KWAD7/AN7 36 PAD6/KWAD6/AN6 35 PAD5/KWAD5/AN5 34 PAD4/KWAD4/AN4 33 PAD11/KWAD11/ACMPM 32 PAD3/KWAD3/AN3 31 PAD10/KWAD10/ACMPP 30 PAD2/KWAD2/AN2 29 PAD9/KWAD9/ACMPO 28 PAD1/KWAD1/AN1 27 PAD8/KWAD8 26 PAD0/KWAD0/AN0 25 Rev.1.23 Freescale Semiconductor ...
Page 65
... PT4 IOC4 21 PT3 IOC3 22 PT2 IOC2 23 PT1 IOC1 24 PT0 IOC0 25 PAD0 KWAD0 26 PAD8 KWAD8 27 PAD1 KWAD1 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — — — — — — — — — ...
Page 66
... DDA V PER1AD/PPS1AD Disabled DDA — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX Rev.1.23 Freescale Semiconductor Reset State — — ...
Page 67
... KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3 BKGD Figure 1-6. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32 Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32 <----lowest-----PRIORITY-----highest----> 2nd Package Pin Pin Func. 1 RESET — Freescale Semiconductor S12GNA16 4 S12GNA32 VSS 48-Pin LQFP/QFN ...
Page 68
... DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor Reset State — — Down — Down Down ...
Page 69
... PS5 MOSI0 45 PS6 SCK0 46 PS7 API_EXTCLK 47 PM0 — 48 PM1 — 1 The regular I/O characteristics (see 1.8.3 S12GN48 1.8.3.1 Pinout 32-Pin LQFP Freescale Semiconductor Function 3rd 4th 5th Func. Func Func AN3 — — ACMPM AN4 — — AN5 — — AN6 — — AN7 — ...
Page 70
... MC9S12G Family Reference Manual, PAD7/KWAD7/AN7/ACMPM PAD6/KWAD6/AN6/ACMPP PAD5/KWAD5/AN5/ACMPO PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 Internal Pull Resistor Power Supply 5th CTRL Func — V PULLUP DDX — — — — — — — — PUCR/PDPEE Rev.1.23 Freescale Semiconductor Reset State — — Down ...
Page 71
... PS1 TXD0 27 PS4 PWM4 28 PS5 IOC4 29 PS6 IOC5 30 PS7 API_EXTCLK 31 PM0 RXD1 32 PM1 TXD1 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — ETRIG0 API_EXTCLK PWM0 ETRIG1 ECLKX2 PWM1 ...
Page 72
... Func. Func Func — — — — — — MC9S12G Family Reference Manual, PAD7/KWAD7/AN7 36 PAD6/KWAD6/AN6 35 PAD5/KWAD5/AN5 34 PAD4/KWAD4/AN4 33 PAD11/KWAD11/AN11/ACMPM 32 PAD3/KWAD3/AN3 31 PAD10/KWAD10/AN10/ACMPP 30 PAD2/KWAD2/AN2 29 PAD9/KWAD9/AN9/ACMPO 28 PAD1/KWAD1/AN1 27 PAD8/KWAD8/AN8 26 PAD0/KWAD0/AN0 25 Internal Pull Resistor Power Supply CTRL V PULLUP DDX — — Rev.1.23 Freescale Semiconductor Reset State — ...
Page 73
... PT0 IOC0 25 PAD0 KWAD0 26 PAD8 KWAD8 27 PAD1 KWAD1 28 PAD9 KWAD9 29 PAD2 KWAD2 30 PAD10 KWAD10 31 PAD3 KWAD3 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — — — — — — — — MISO1 — ...
Page 74
... DDA V PER1AD/PPS1AD Disabled DDA — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX Rev.1.23 Freescale Semiconductor Reset State — — ...
Page 75
... KWJ4/PJ4 RESET VDDX VDDR VSSX EXTAL/PE0 VSS XTAL/PE1 10 TEST 11 MISO1/KWJ0/PJ0 12 MOSI1/KWJ1/PJ1 13 SCK1/KWJ2/PJ2 14 SS1/KWJ3/PJ3 15 BKGD 16 Figure 1-9. 64-Pin LQFP Pinout for S12GN48 Freescale Semiconductor S12GN48 64-Pin LQFP MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family 48 PAD15/KWAD15 47 PAD7/KWAD7/AN7 46 PAD14/KWAD14 45 PAD6/KWAD6/AN6 ...
Page 76
... DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX Rev.1.23 Freescale Semiconductor — — — — ...
Page 77
... VRH — 50 VDDA — 51 VSSA — 52 PS0 RXD0 53 PS1 TXD0 54 PS2 RXD1 55 PS3 TXD1 56 PS4 MISO0 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — — IRQ — — XIRQ — — AN0 — ...
Page 78
... Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual, Internal Pull Resistor Power Supply Reset CTRL State V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERJ/PPSJ DDX Rev.1.23 Freescale Semiconductor ...
Page 79
... Pinout 32-Pin LQFP VRH/VDDXRA EXTAL/PE0 XTAL/PE1 Figure 1-10. 32-Pin LQFP Pinout for S12G48 and S12G64 Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64 <----lowest-----PRIORITY-----highest----> 2nd Package Pin Pin Func. 1 RESET — Freescale Semiconductor RESET S12G48 23 VSSXA 3 22 S12G64 4 21 VSS ...
Page 80
... PER1AD/PPS1AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX Rev.1.23 Freescale Semiconductor Reset State — — Down — Down Down ...
Page 81
... Pinout 48-Pin LQFP RESET VDDXR VSSX EXTAL/PE0 XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD Figure 1-11. 48-Pin LQFP Pinout for S12G48 and S12G64 Freescale Semiconductor Function 3rd 4th Func. Func Func RXCAN — TXCAN — Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled ...
Page 82
... DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA Rev.1.23 Freescale Semiconductor Reset State — — Down — Down Down ...
Page 83
... PS3 TXD1 43 PS4 MISO0 44 PS5 MOSI0 45 PS6 SCK0 46 PS7 API_EXTCLK 47 PM0 RXCAN 48 PM1 TXCAN 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func AN9 ACMPO — AN2 — — AN10 ACMPP AN3 — — AN11 ACMPM AN4 — ...
Page 84
... SS1/KWJ3/PJ3 15 BKGD 16 Figure 1-12. 64-Pin LQFP Pinout for S12G48 and S12G64 S12G48 7 S12G64 8 9 64-pin LQFP MC9S12G Family Reference Manual, 48 PAD15/KWAD15 47 PAD7/KWAD7/AN7 46 PAD14/KWAD14 45 PAD6/KWAD6/AN6 44 PAD13/KWAD13 43 PAD5/KWAD5/AN5 42 PAD12/KWAD12 41 PAD4/KWAD4/AN4 40 PAD11/KWAD11/AN11/ACMPM 39 PAD3/KWAD3/AN3 38 PAD10/KWAD10/AN10/ACMPP 37 PAD2/KWAD2/AN2 36 PAD9/KWAD9/AN9/ACMPO 35 PAD1/KWAD1/AN1 34 PAD8/KWAD8/AN8 33 PAD0/KWAD0/AN0 Rev.1.23 Freescale Semiconductor ...
Page 85
... PP3 KWP3 21 PP4 KWP4 22 PP5 KWP5 23 PP6 KWP6 24 PP7 KWP7 25 PT7 — 26 PT6 — 27 PT5 IOC5 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — — — — — — — — — ...
Page 86
... Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA — — — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX Rev.1.23 Freescale Semiconductor — — — ...
Page 87
... PS6 SCK0 59 PS7 API_EXTCLK 60 PM0 RXCAN 61 PM1 TXCAN 62 PM2 — 63 PM3 — 64 PJ7 KWJ7 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — ECLK SS0 — — — — — — ...
Page 88
... Function 3rd 4th 5th Func. Func Func — — — MC9S12G Family Reference Manual, PAD7/KWAD7/AN7 36 PAD6/KWAD6/AN6 35 PAD5/KWAD5/AN5 34 PAD4/KWAD4/AN4 33 PAD11/KWAD11/AN11/ACMPM 32 PAD3/KWAD3/AN3 31 PAD10/KWAD10/AN10/ACMPP 30 PAD2/KWAD2/AN2 29 PAD9/KWAD9/AN9/ACMPO 28 PAD1/KWAD1/AN1 27 PAD8/KWAD8/AN8 26 PAD0/KWAD0/AN0 25 Internal Pull Resistor Power Supply CTRL V PULLUP DDX Rev.1.23 Freescale Semiconductor Reset State ...
Page 89
... PT1 IOC1 24 PT0 IOC0 25 PAD0 KWAD0 26 PAD8 KWAD8 27 PAD1 KWAD1 28 PAD9 KWAD9 29 PAD2 KWAD2 30 PAD10 KWAD10 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — — — — — — — — — ...
Page 90
... DDA V PER1AD/PPS1AD Disabled DDA — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX Rev.1.23 Freescale Semiconductor Reset State — — ...
Page 91
... VDDX VDDR VSSX EXTAL/PE0 VSS XTAL/PE1 10 TEST 11 MISO1/KWJ0/PJ0 12 MOSI1/KWJ1/PJ1 13 SCK1/KWJ2/PJ2 14 SS1/KWJ3/PJ3 15 BKGD 16 Figure 1-14. 64-Pin LQFP Pinout for S12GA48 and S12GA64 Freescale Semiconductor S12GA48 7 S12GA64 8 9 64-pin LQFP MC9S12G Family Reference Manual, Rev.1.23 Device Overview MC9S12G-Family 48 PAD15/KWAD15 47 PAD7/KWAD7/AN7 46 PAD14/KWAD14 ...
Page 92
... DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERP/PPSP Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX Rev.1.23 Freescale Semiconductor — — — — ...
Page 93
... VRH — 50 VDDA — 51 VSSA — 52 PS0 RXD0 53 PS1 TXD0 54 PS2 RXD1 55 PS3 TXD1 56 PS4 MISO0 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — — — — IRQ — — XIRQ — — AN0 — ...
Page 94
... Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual, Internal Pull Resistor Power Supply Reset CTRL State V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERJ/PPSJ DDX Rev.1.23 Freescale Semiconductor ...
Page 95
... MISO1/PWM6/KWJ0/PJ0 MOSI1/IOC6/KWJ1/PJ1 SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3 BKGD Figure 1-15. 48-Pin LQFP Pinout for S12G96 and S12G128 Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128 <----lowest-----PRIORITY-----highest----> 2nd Package Pin Pin Func. 1 RESET — Freescale Semiconductor S12G96 4 S12G128 VSS 48-Pin LQFP ...
Page 96
... DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor Reset State — — Down — Down Down ...
Page 97
... PS3 TXD1 43 PS4 MISO0 44 PS5 MOSI0 45 PS6 SCK0 46 PS7 API_EXTCLK 47 PM0 RXD2 48 PM1 TXD2 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func AN3 — — AN11 — — AN4 — — AN5 — — AN6 — ...
Page 98
... BKGD 16 Figure 1-16. 64-Pin LQFP Pinout for S12G96 and S12G128 100 S12G96 7 S12G128 8 9 64-Pin LQFP MC9S12G Family Reference Manual, 48 PAD15/KWAD15 47 PAD7/KWAD7/AN7 46 PAD14/KWAD14 45 PAD6/KWAD6/AN6 44 PAD13/KWAD13 43 PAD5/KWAD5/AN5 42 PAD12/KWAD12 41 PAD4/KWAD4/AN4 40 PAD11/KWAD11/AN11 39 PAD3/KWAD3/AN3 38 PAD10/KWAD10/AN10 37 PAD2/KWAD2/AN2 36 PAD9/KWAD9/AN9 35 PAD1/KWAD1/AN1 34 PAD8/KWAD8/AN8 33 PAD0/KWAD0/AN0 Rev.1.23 Freescale Semiconductor ...
Page 99
... PP3 KWP3 21 PP4 KWP4 22 PP5 KWP5 23 PP6 KWP6 24 PP7 KWP7 25 PT7 IOC7 26 PT6 IOC6 27 PT5 IOC5 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func SCK2 — — MOSI2 — — MISO2 — — — — — — — — — ...
Page 100
... Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA — — — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX Rev.1.23 Freescale Semiconductor — — — ...
Page 101
... PS6 SCK0 59 PS7 API_EXTCLK 60 PM0 RXCAN 61 PM1 TXCAN 62 PM2 RXD2 63 PM3 TXD2 64 PJ7 KWJ7 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — ECLK SS0 — — — — — — ...
Page 102
... Figure 1-17. 100-Pin LQFP Pinout for S12G96 and S12G128 104 S12G96 S12G128 100-Pin LQFP MC9S12G Family Reference Manual, 75 VRH 74 PC7 73 PC6 72 PC5 71 PC4 70 PAD15/KWAD15/ 69 PAD7/KWAD7/AN7 68 PAD14/KWAD14 67 PAD6/KWAD6/AN6 66 PAD13/KWAD13 65 PAD5/KWAD5/AN5 64 PAD12/KWAD12 63 PAD4/KWAD4/AN4 62 PAD11/KWAD11/AN11 61 PAD3/KWAD3/AN3 60 PAD10/KWAD10/AN10 59 PAD2/KWAD2/AN2 58 PAD9/KWAD9/AN9 57 PAD1/KWAD1/AN1 56 PAD8/KWAD8/AN8 55 PAD0/KWAD0/AN0 54 PC3 53 PC2 52 PC1 51 PC0 Rev.1.23 Freescale Semiconductor ...
Page 103
... PA4 17 PA5 18 PA6 19 PA7 20 PJ0 21 PJ1 22 PJ2 23 PJ3 24 BKGD 25 PB0 26 PB1 API_EXTCLK 27 PB2 ECLKX2 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. KWJ6 SCK2 — KWJ5 MOSI2 — KWJ4 MISO2 — — — — — — — — — — ...
Page 104
... Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor ...
Page 105
... PC6 74 PC7 75 VRH 76 VDDA 77 VSSA 78 PD0 79 PD1 80 PD2 81 PD3 82 PS0 83 PS1 84 PS2 85 PS3 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. AN1 — AN9 — AN2 — AN10 — AN3 — AN11 — AN4 — — — AN5 — — ...
Page 106
... PERS/PPSS Up DDX V PERS/PPSS Up DDX V PERS/PPSS Up DDX — — — — — — V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERJ/PPSJ Up DDX Rev.1.23 Freescale Semiconductor ...
Page 107
... MISO1/PWM6/KWJ0/PJ0 MOSI1/IOC6/KWJ1/PJ1 SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3 BKGD Figure 1-18. 48-Pin LQFP Pinout for S12GA96 and S12GA128 Table 1-23. 48-Pin LQFP Pinout for S12GA96 and S12GA128 <----lowest-----PRIORITY-----highest----> 2nd Package Pin Pin Func. 1 RESET — Freescale Semiconductor S12GA96 4 S12GA128 VSS 48-Pin LQFP ...
Page 108
... DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor Reset State — — Down — Down Down ...
Page 109
... PS3 TXD1 43 PS4 MISO0 44 PS5 MOSI0 45 PS6 SCK0 46 PS7 API_EXTCLK 47 PM0 RXD2 48 PM1 TXD2 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func AN3 — — AN11 — — AN4 — — AN5 — — AN6 — ...
Page 110
... BKGD 16 Figure 1-19. 64-Pin LQFP Pinout for S12GA96 and S12GA128 112 S12GA96 7 S12GA128 8 9 64-Pin LQFP MC9S12G Family Reference Manual, 48 PAD15/KWAD15 47 PAD7/KWAD7/AN7 46 PAD14/KWAD14 45 PAD6/KWAD6/AN6 44 PAD13/KWAD13 43 PAD5/KWAD5/AN5 42 PAD12/KWAD12 41 PAD4/KWAD4/AN4 40 PAD11/KWAD11/AN11 39 PAD3/KWAD3/AN3 38 PAD10/KWAD10/AN10 37 PAD2/KWAD2/AN2 36 PAD9/KWAD9/AN9 35 PAD1/KWAD1/AN1 34 PAD8/KWAD8/AN8 33 PAD0/KWAD0/AN0 Rev.1.23 Freescale Semiconductor ...
Page 111
... PP3 KWP3 21 PP4 KWP4 22 PP5 KWP5 23 PP6 KWP6 24 PP7 KWP7 25 PT7 IOC7 26 PT6 IOC6 27 PT5 IOC5 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func SCK2 — — MOSI2 — — MISO2 — — — — — — — — — ...
Page 112
... Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA — — — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX Rev.1.23 Freescale Semiconductor — — — ...
Page 113
... PS6 SCK0 59 PS7 API_EXTCLK 60 PM0 RXCAN 61 PM1 TXCAN 62 PM2 RXD2 63 PM3 TXD2 64 PJ7 KWJ7 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — ECLK SS0 — — — — — — ...
Page 114
... Figure 1-20. 100-Pin LQFP Pinout for S12GA96 and S12GA128 116 S12GA96 S12GA128 100-Pin LQFP MC9S12G Family Reference Manual, 75 VRH 74 PC7 73 PC6 72 PC5 71 PC4 70 PAD15/KWAD15/ 69 PAD7/KWAD7/AN7 68 PAD14/KWAD14 67 PAD6/KWAD6/AN6 66 PAD13/KWAD13 65 PAD5/KWAD5/AN5 64 PAD12/KWAD12 63 PAD4/KWAD4/AN4 62 PAD11/KWAD11/AN11 61 PAD3/KWAD3/AN3 60 PAD10/KWAD10/AN10 59 PAD2/KWAD2/AN2 58 PAD9/KWAD9/AN9 57 PAD1/KWAD1/AN1 56 PAD8/KWAD8/AN8 55 PAD0/KWAD0/AN0 54 PC3 53 PC2 52 PC1 51 PC0 Rev.1.23 Freescale Semiconductor ...
Page 115
... PA4 17 PA5 18 PA6 19 PA7 20 PJ0 21 PJ1 22 PJ2 23 PJ3 24 BKGD 25 PB0 26 PB1 API_EXTCLK 27 PB2 ECLKX2 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. KWJ6 SCK2 — KWJ5 MOSI2 — KWJ4 MISO2 — — — — — — — — — — ...
Page 116
... Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor ...
Page 117
... PC6 74 PC7 75 VRH 76 VDDA 77 VSSA 78 PD0 79 PD1 80 PD2 81 PD3 82 PS0 83 PS1 84 PS2 85 PS3 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. AN1 — AN9 — AN2 — AN10 — AN3 — AN11 — AN4 — — — AN5 — — ...
Page 118
... PERS/PPSS Up DDX V PERS/PPSS Up DDX V PERS/PPSS Up DDX — — — — — — V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERJ/PPSJ Up DDX Rev.1.23 Freescale Semiconductor ...
Page 119
... MISO1/PWM6/KWJ0/PJ0 MOSI1/IOC6/KWJ1/PJ1 SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3 BKGD Figure 1-21. 48-Pin LQFP Pinout for S12G192 and S12G240 Table 1-26. 48-Pin LQFP Pinout for S12G192 and S12G240 <----lowest-----PRIORITY-----highest----> 2nd Package Pin Pin Func. 1 RESET — Freescale Semiconductor S12G192 4 S12G240 VSS 48-Pin LQFP ...
Page 120
... DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor Reset State — — Down — Down Down ...
Page 121
... PS3 TXD1 43 PS4 MISO0 44 PS5 MOSI0 45 PS6 SCK0 46 PS7 API_EXTCLK 47 PM0 RXD2 48 PM1 TXD2 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func AN3 — — AN11 — — AN4 — — AN5 — — AN6 — ...
Page 122
... BKGD 16 Figure 1-22. 64-Pin LQFP Pinout for S12G192 and S12G240 124 S12G192 7 S12G240 8 9 64-Pin LQFP MC9S12G Family Reference Manual, 48 PAD15/KWAD15/AN15 47 PAD7/KWAD7/AN7 46 PAD14/KWAD14/AN14 45 PAD6/KWAD6/AN6 44 PAD13/KWAD13/AN13 43 PAD5/KWAD5/AN5 42 PAD12/KWAD12/AN12 41 PAD4/KWAD4/AN4 40 PAD11/KWAD11/AN11 39 PAD3/KWAD3/AN3 38 PAD10/KWAD10/AN10 37 PAD2/KWAD2/AN2 36 PAD9/KWAD9/AN9 35 PAD1/KWAD1/AN1 34 PAD8/KWAD8/AN8 33 PAD0/KWAD0/AN0 Rev.1.23 Freescale Semiconductor ...
Page 123
... PP3 KWP3 21 PP4 KWP4 22 PP5 KWP5 23 PP6 KWP6 24 PP7 KWP7 25 PT7 IOC7 26 PT6 IOC6 27 PT5 IOC5 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func SCK2 — — MOSI2 — — MISO2 — — — — — — — — — ...
Page 124
... Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA — — — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX Rev.1.23 Freescale Semiconductor — — — ...
Page 125
... PS6 SCK0 59 PS7 API_EXTCLK 60 PM0 RXCAN 61 PM1 TXCAN 62 PM2 RXD2 63 PM3 TXD2 64 PJ7 KWJ7 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — ECLK SS0 — — — — — — ...
Page 126
... Figure 1-23. 100-Pin LQFP Pinout for S12G192 and S12G240 128 S12G192 S12G240 100-Pin LQFP MC9S12G Family Reference Manual, 75 VRH 74 PC7 73 PC6 72 PC5 71 PC4 70 PAD15/KWAD15/AN15 69 PAD7/KWAD7/AN7 68 PAD14/KWAD14/AN14 67 PAD6/KWAD6/AN6 66 PAD13/KWAD13/AN13 65 PAD5/KWAD5/AN5 64 PAD12/KWAD12/AN12 63 PAD4/KWAD4/AN4 62 PAD11/KWAD11/AN11 61 PAD3/KWAD3/AN3 60 PAD10/KWAD10/AN10 59 PAD2/KWAD2/AN2 58 PAD9/KWAD9/AN9 57 PAD1/KWAD1/AN1 56 PAD8/KWAD8/AN8 55 PAD0/KWAD0/AN0 54 PC3 53 PC2 52 PC1 51 PC0 Rev.1.23 Freescale Semiconductor ...
Page 127
... PA4 17 PA5 18 PA6 19 PA7 20 PJ0 21 PJ1 22 PJ2 23 PJ3 24 BKGD 25 PB0 26 PB1 API_EXTCLK 27 PB2 ECLKX2 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. KWJ6 SCK2 — KWJ5 MOSI2 — KWJ4 MISO2 — — — — — — — — — — ...
Page 128
... Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor ...
Page 129
... PC6 74 PC7 75 VRH 76 VDDA 77 VSSA 78 PD0 79 PD1 80 PD2 81 PD3 82 PS0 83 PS1 84 PS2 85 PS3 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. AN1 — AN9 — AN2 — AN10 — AN3 — AN11 — AN4 — AN12 — AN5 — AN13 — ...
Page 130
... PERS/PPSS Up DDX V PERS/PPSS Up DDX V PERS/PPSS Up DDX — — — — — — V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERJ/PPSJ Up DDX Rev.1.23 Freescale Semiconductor ...
Page 131
... MISO1/PWM6/KWJ0/PJ0 MOSI1/IOC6/KWJ1/PJ1 SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3 BKGD Figure 1-24. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Table 1-29. 48-Pin LQFP Pinout for S12GA192 and S12GA240 <----lowest-----PRIORITY-----highest----> 2nd Package Pin Pin Func. 1 RESET — Freescale Semiconductor S12GA192 4 S12GA240 VSS 48-Pin LQFP ...
Page 132
... DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor Reset State — — Down — Down Down ...
Page 133
... PS3 TXD1 43 PS4 MISO0 44 PS5 MOSI0 45 PS6 SCK0 46 PS7 API_EXTCLK 47 PM0 RXD2 48 PM1 TXD2 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func AN3 — — AN11 DACU0 AMP0 AN4 — — AN5 — — AN6 — ...
Page 134
... BKGD 16 Figure 1-25. 64-Pin LQFP Pinout for S12GA192 and S12GA240 136 S12GA192 7 S12GA240 8 9 64-Pin LQFP MC9S12G Family Reference Manual, 48 PAD15/KWAD15/AN15/DACU0 47 PAD7/KWAD7/AN7 46 PAD14/KWAD14/AN14/AMPP0 45 PAD6/KWAD6/AN6 44 PAD13/KWAD13/AN13/AMPM0 43 PAD5/KWAD5/AN5 42 PAD12/KWAD12/AN12 41 PAD4/KWAD4/AN4 40 PAD11/KWAD11/AN11/AMP0 39 PAD3/KWAD3/AN3 38 PAD10/KWAD10/AN10/DACU1/AMP1 37 PAD2/KWAD2/AN2 36 PAD9/KWAD9/AN9 35 PAD1/KWAD1/AN1 34 PAD8/KWAD8/AN8 33 PAD0/KWAD0/AN0 Rev.1.23 Freescale Semiconductor ...
Page 135
... PP3 KWP3 21 PP4 KWP4 22 PP5 KWP5 23 PP6 KWP6 24 PP7 KWP7 25 PT7 IOC7 26 PT6 IOC6 27 PT5 IOC5 Freescale Semiconductor Function 3rd 4th 5th Func. Func Func SCK2 — — MOSI2 — — MISO2 — — — — — — — — — ...
Page 136
... Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA — — — — — — V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX V PERS/PPSS DDX Rev.1.23 Freescale Semiconductor — — — ...
Page 137
... PS6 SCK0 59 PS7 API_EXTCLK 60 PM0 RXCAN 61 PM1 TXCAN 62 PM2 RXD2 63 PM3 TXD2 64 PJ7 KWJ7 1 The regular I/O characteristics (see Freescale Semiconductor Function 3rd 4th 5th Func. Func Func — — — — — — ECLK SS0 — — — — — — ...
Page 138
... Figure 1-26. 100-Pin LQFP Pinout for S12GA192 and S12GA240 140 S12GA192 S12GA240 100-Pin LQFP MC9S12G Family Reference Manual, 75 VRH 74 PC7/DACU1 73 PC6/AMPP1 72 PC5/AMPM1 71 PC4 70 PAD15/KWAD15/AN15/DACU0 69 PAD7/KWAD7/AN7 68 PAD14/KWAD14/AN14/AMPP0 67 PAD6/KWAD6/AN6 66 PAD13/KWAD13/AN13/AMPM0 65 PAD5/KWAD5/AN5 64 PAD12/KWAD12/AN12 63 PAD4/KWAD4/AN4 62 PAD11/KWAD11/AN11/AMP0 61 PAD3/KWAD3/AN3 60 PAD10/KWAD10/AN10/AMP1 59 PAD2/KWAD2/AN2 58 PAD9/KWAD9/AN9 57 PAD1/KWAD1/AN1 56 PAD8/KWAD8/AN8 55 PAD0/KWAD0/AN0 54 PC3 53 PC2 52 PC1 51 PC0 Rev.1.23 Freescale Semiconductor ...
Page 139
... PA4 17 PA5 18 PA6 19 PA7 20 PJ0 21 PJ1 22 PJ2 23 PJ3 24 BKGD 25 PB0 26 PB1 API_EXTCLK 27 PB2 ECLKX2 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. KWJ6 SCK2 — KWJ5 MOSI2 — KWJ4 MISO2 — — — — — — — — — — ...
Page 140
... Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor ...
Page 141
... AMPP1 74 PC7 DACU1 75 VRH 76 VDDA 77 VSSA 78 PD0 79 PD1 80 PD2 81 PD3 82 PS0 83 PS1 84 PS2 85 PS3 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. AN1 — AN9 — AN2 — AN10 AMP1 AN3 — AN11 AMP0 AN4 — AN12 — AN5 — ...
Page 142
... PERS/PPSS Up DDX V PERS/PPSS Up DDX V PERS/PPSS Up DDX — — — — — — V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERJ/PPSJ Up DDX Rev.1.23 Freescale Semiconductor ...
Page 143
... PA4 17 PA5 18 PA6 19 PA7 20 PJ0 21 PJ1 22 PJ2 23 PJ3 24 BKGD 25 PB0 26 PB1 API_EXTCLK 27 PB2 ECLKX2 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. KWJ6 SCK2 — KWJ5 MOSI2 — KWJ4 MISO2 — — — — — — — — — — ...
Page 144
... Disabled DDX V PERT/PPST Disabled DDX V PERT/PPST Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPBE Disabled DDX V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PUCR/PUPCE Disabled DDA V PER1AD/PPS1AD Disabled DDA V PER0AD/PPS0AD Disabled DDA Rev.1.23 Freescale Semiconductor ...
Page 145
... AMPP1 74 PC7 DACU1 75 VRH 76 VDDA 77 VSSA 78 PD0 79 PD1 80 PD2 81 PD3 82 PS0 83 PS1 84 PS2 85 PS3 Freescale Semiconductor Function 2nd 3rd 4th Func. Func. Func. AN1 — AN9 — AN2 — AN10 AMP1 AN3 — AN11 AMP0 AN4 — AN12 — AN5 — ...
Page 146
... V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PUCR/PUPDE Disabled DDX V PERM/PPSM Disabled DDX V PERM/PPSM Disabled DDX V PERJ/PPSJ Up DDX MC9S12G-Family”. 1.10.1 Chip Configuration Summary. Rev.1.23 Freescale Semiconductor ...
Page 147
... Consult the S12 CPU manual and the S12SINT section for information on exception processing. 1.12.1 Resets Table 1-34. lists all Reset sources and the vector locations. Resets are explained in detail in the “S12 Clock, Reset and Power Management Unit Freescale Semiconductor Table 1-33. Chip Modes Chip Modes MODC Normal single chip Special single chip “ ...
Page 148
... TIE (C4I) No TIE (C5I) No TIE (C6I) No TIE (C7I) No TSCR2 (TOI) No PACTL (PAOVI) No PACTL (PAI SCI0CR2 Yes SCI1CR2 Yes Rev.1.23 Freescale Semiconductor Wakeup from WAIT - - Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...
Page 149
... Port AD interrupt Vector base + $80 Spurious interrupt 1 16 bits vector address based 2 Only available if the 8 channel timer module is instantiated on the device 3 Only available if the 8 channel timer module is instantiated on the device Freescale Semiconductor CCR Mask ADC I bit ATDCTL2 (ASCIE) Reserved Port J I bit ...
Page 150
... Table 1-37 Table 1-36. Initial COP Rate Configuration NV[2:0] in CR[2:0] in CPMUCOP Register 000 001 010 011 100 101 110 111 MC9S12G Family Reference Manual, Section 29.1, “Introduction”. for coding. The FOPT register is 111 110 101 100 011 010 001 000 Rev.1.23 Freescale Semiconductor ...
Page 151
... The ADC temperature sensor is only available on S12GA192 and S12GA240 devices. 1. See Chapter 10, “S12 Clock, Reset and Power Management Unit 2. See Section 10.3.2.15, “Autonomous Clock Trimming Register Freescale Semiconductor Table 1-37. Initial WCOP Configuration NV[3] in WCOP in CPMUCOP Register 1 0 describes the connection of the external trigger inputs. Consult the Table 13-15) ...
Page 152
... Result of channel “Internal_0” conversion Value in IFR locatio 0x0_4022/0x0_4023 ADC resolution (10 bit) CAUTION reference conversion, the NVMs must DDF CAUTION must remain at a constant level RH MC9S12G Family Reference Manual, (see Table 1-38). V DDF (see Table DDF • • n • Rev.1.23 Freescale Semiconductor DDF 1-38) and ...
Page 153
... S12GN16, S12GNA16, S12GN32, S12GNA32, S12GN48, S12G48, VRH VSSA VRH VSSA Figure 1-27. ADC VRH/VRL Signal Connection 1.19 BDM Clock Source Connectivity The BDM clock is mapped to the VCO clock divided by four. Freescale Semiconductor S12GA48, S12G64, S12GA64, S12G96, S12GA96, S12G128, S12GA128, S12G192, S12G240 S12GA192, S12GA240 RVA VRH VRH_INT VRL_INT VSSA MC9S12G Family Reference Manual, Rev ...
Page 154
... Device Overview MC9S12G-Family 156 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 155
... Glossary Term Pin Signal Freescale Semiconductor Substantial Change(s) • Removed TXD2 and RXD2 from PM1 and PM0 for G64 • Simplified input buffer control description on port C and AD • Corrected DAC signal priorities on pins PAD10 and PAD11 with shared AMP and DACU output functions • ...
Page 156
... Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages. 158 Group of general-purpose I/O pins sharing peripheral signals Table 2-2. Table 2-2. Device Groups Devices with same set of package options ,S12GN48 1,2 1,2 MC9S12G Family Reference Manual, Definition Rev.1.23 Freescale Semiconductor ...
Page 157
... Table 2-3 shows the availability of I/O port pins for each group in the largest offered package option. Table 2-3. Port Pin Availability (in largest package) per Device Port A B Freescale Semiconductor Figure 2-1. Block Diagram Pin Enable, Data Pin Enable, Data Package Code Pin Routing (20 TSSOP only) ...
Page 158
... PORT/PT not listed representative for any other port related register bit with the same 160 Device Group G1 G2 (100 pin) (64 pin) 7-0 - 7-0 - 1-0 1-0 7-0 7-0 7-0 7-0 3-0 3-0 7-0 7-0 7-0 7-0 15-0 15-0 (PKGCR)”). The related value is loaded from a factory MC9S12G Family Reference Manual, G3 (48 pin 1-0 5-0 7-0 1-0 5-0 3-0 11-0 Rev.1.23 Freescale Semiconductor ...
Page 159
... PT0AD; other related register bits of this pin are PTI0AD7, DDR0AD7, PER0AD7, PPS0AD7, PIE0AD7 and PIF0AD7. If there is more than one signal associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). Freescale Semiconductor NOTE MC9S12G Family Reference Manual, Rev.1.23 Port Integration Module (S12GPIMV1) Section 2.4, “PIM Ports - ...
Page 160
... I/O GPIO I Maskable level- or falling-edge sensitive interrupt I/O GPIO I/O GPIO O Free-running clock (ECLK x 2) I/O GPIO O API Clock I/O GPIO O Free-running clock I/O GPIO O DAC1 output unbuffered I/O GPIO I DAC1 non-inv. input (+) I/O GPIO I DAC1 inverting input (-) I/O GPIO I ADC analog I/O GPIO I ADC analog I/O GPIO I/O GPIO Rev.1.23 Freescale Semiconductor ...
Page 161
... IOC0 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ I/O GPIO [PTT0] Freescale Semiconductor Table 2-4. Signals and Priorities Signals per Device and Package (signal priority on pin from top to bottom) ...
Page 162
... I/O Timer channel ❏ ❏ I/O Timer channel ❍ ❍ I SCI receive pin ■ ■ ■ ■ O PWM channel ❏ ❏ O PWM channel ❏ ❏ I ADC external trigger I/O SCI transmit I/O GPIO I SCI receive I/O GPIO I/O SCI transmit I/O GPIO I SCI receive I/O GPIO Rev.1.23 Freescale Semiconductor ...
Page 163
... RXCAN RXD2 RXD1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ [PTM0] Freescale Semiconductor Table 2-4. Signals and Priorities Signals per Device and Package (signal priority on pin from top to bottom) 100 ...
Page 164
... I/O GPIO with interrupt O PWM channel I/O GPIO with interrupt O PWM channel I ADC external trigger I/O GPIO with interrupt O PWM channel O Free-running clock (ECLK ADC external trigger I/O GPIO with interrupt O PWM channel O API Clock I ADC external trigger I/O GPIO with interrupt Rev.1.23 Freescale Semiconductor ...
Page 165
... PJ0 MISO1 PWM6 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ [PTJ0]/ KWJ0 Freescale Semiconductor Table 2-4. Signals and Priorities Signals per Device and Package (signal priority on pin from top to bottom) 100 64 48 ■ ...
Page 166
... DAC0 output unbuffered I ACMP inverting input (-) I ADC analog I/O GPIO with interrupt O DAC1 output buffered O DAC1 output unbuffered I ACMP non-inv. input (+) I ADC analog I/O GPIO with interrupt O ACMP unsync. dig. out I ADC analog I/O GPIO with interrupt I ADC analog I/O GPIO with interrupt Rev.1.23 Freescale Semiconductor ...
Page 167
... I/O GPIO with interrupt [PT1AD2: PT1AD0]/ KWAD2- KWAD0 Freescale Semiconductor Table 2-4. Signals and Priorities Signals per Device and Package (signal priority on pin from top to bottom) 100 ...
Page 168
... Here SignalA has priority over SignalB and general-purpose output function (GPO; represented by related port data register bit). The general-purpose output is always of lowest priority if no other signal is enabled. Peripheral input signals on shared pins are always connected monitoring the pin level independent of their use. 170 MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 169
... ECLK signal forces the I/O state to an output. • Signal priority: 100 LQFP: ECLK > GPO 2.3.4 Pins PC7-0 • When using AMPM1, AMPP1 or DACU1 please refer to section “Initialization”. Freescale Semiconductor Table 2-5. Pin BKGD Table 2-6. Port A Pins PA7-0 Table 2-7. Port B Pins PB7-0 NOTE MC9S12G Family Reference Manual, Rev ...
Page 170
... The routed ADC function has no effect on the output state. Refer to • Signal priority: 100 LQFP: GPO 172 Table 2-8. Port C Pins PC7-0 NOTE/2-171 for input buffer control. NOTE/2-171 for input buffer control. MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 171
... If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can still be used as general-purpose I timer output. The use case for the ACMP timer link requires the timer input capture function to be enabled. • Signal priority: 48/64/100 LQFP: IOC5 > GPO Freescale Semiconductor Table 2-9. Port D Pins PD7-0 Table 2-10. Port ...
Page 172
... The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state output for a timer port associated with an enabled output compare. • Signal priority: 100 LQFP: IOC0 > GPO Others: XIRQ > IOC0 > GPO 174 Table 2-11. Port T Pins PT7-0 (continued) MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor ...
Page 173
... I/O state will be forced to output. • Signal priority: 20 TSSOP: MOSI0 > IOC2 > GPO 32 LQFP: MOSI0 > IOC4 > GPO Others: MOSI0 > GPO Freescale Semiconductor Table 2-12. Port S Pins PS7-0 MC9S12G Family Reference Manual, Rev.1.23 Port Integration Module (S12GPIMV1) Section 2.6.4, “ ...
Page 174
... Except 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled the I/O state will be forced to be input. • Signal priority: 20 TSSOP: GPO Others: RXD0 > GPO 176 Table 2-12. Port S Pins PS7-0 (continued) MC9S12G Family Reference Manual, Section 2.6.4, “ADC External Rev.1.23 Freescale Semiconductor ...
Page 175
... LQFP: The PWM channels 5 and 4 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state output. • 48/64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48/64/100 LQFP: PWM > GPO Freescale Semiconductor Table 2-13. Port M Pins PM3-0 Table 2-14. Port ...
Page 176
... Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: Except 100 LQFP and 20 TSSOP: PWM0 > API_EXTCLK > GPO 100 LQFP: PWM0 > GPO 178 Table 2-14. Port P Pins PP7-0 (continued) ETRIG3-0”. ETRIG3-0”. ETRIG3-0”. MC9S12G Family Reference Manual, Section 2.6.4, Section 2.6.4, “ADC Section 2.6.4, “ADC Rev.1.23 Freescale Semiconductor ...
Page 177
... I/O state output for a timer port associated with an enabled output. • Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48 LQFP: SCK1 > IOC7 > GPO 64/100 LQFP: SCK1 > GPO Freescale Semiconductor Table 2-15. Port J Pins PJ7-0 MC9S12G Family Reference Manual, Rev.1.23 ...
Page 178
... Taking the availability of the different sources on each pin into account the following logic equation must be true to activate the digital input buffer for general-purpose input use: IBEx = ( (ATDDIENH/L[IENx]=1) OR (ATDCTL1[ETRIGSEL]=0 AND ATDCTL2[ETRIGE]=1) OR (PRR1[PRR1AN]=1) ) AND (ACDIEN=1) 180 Table 2-15. Port J Pins PJ7-0 (continued) NOTE MC9S12G Family Reference Manual, Rev.1.23 Freescale Semiconductor Eqn. 2-1 ...
Page 179
... The ADC function has no effect on the output state. Refer to buffer control. • 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 64/100 LQFP: GPO Freescale Semiconductor Table 2-16. Port AD Pins AD15-8 NOTE/2-180 for input buffer control. ...
Page 180
... LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 48/64 LQFP: AMP1 > DACU1 > GPO 100 LQFP: AMP1 > GPO 182 Table 2-16. Port AD Pins AD15-8 NOTE/2-180 for input buffer control. NOTE/2-180 for input buffer control. MC9S12G Family Reference Manual “operational 1 or “operational Rev.1.23 Freescale Semiconductor ...
Page 181
... Except 20 TSSOP: The ADC analog input channel signal AN6 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to buffer control. • Except 20 TSSOP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: Except 20 TSSOP: GPO Freescale Semiconductor Table 2-16. Port AD Pins AD15-8 Table 2-17. Port AD Pins AD7-0 MC9S12G Family Reference Manual, Rev ...
Page 182
... Signal priority: 20 TSSOP: RXD0 > IOC2 > PWM2 > GPO Others: GPO 184 Table 2-17. Port AD Pins AD7-0 (continued) MC9S12G Family Reference Manual, NOTE/2-180 for input buffer control. Section 2.6.4, “ADC External NOTE/2-180 for input buffer control. Section 2.6.4, “ADC External Rev.1.23 Freescale Semiconductor ...
Page 183
... The ADC analog input channel signals AN2-0 and their related digital trigger inputs are mapped to this pin. The ADC function has no effect on the output state. Refer to • Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: GPO Freescale Semiconductor Table 2-17. Port AD Pins AD7-0 (continued) MC9S12G Family Reference Manual, Rev.1.23 ...
Page 184
... MC9S12G Family Reference Manual, Table 2-2). Addresses 0x0000 to Access Reset Value Section/Page R/W 0x00 2.4.3.1/2-205 R/W 0x00 2.4.3.2/2-205 R/W 0x00 2.4.3.3/2-206 R/W 0x00 2.4.3.4/2-207 R/W 0x00 2.4.3.5/2-207 R/W 0x00 2.4.3.6/2-208 R/W 0x00 2.4.3.7/2-209 R/W 0x00 2.4.3.8/2-209 R/W 0x00 R/W 0x00 - - R/W 0x50 2.4.3.11/2-211 R 0x00 - - R/W 0xC0 2.4.3.12/2-213 R 0x00 R/W 0x00 2.4.3.13/2-213 R 0x00 - - Rev.1.23 Freescale Semiconductor - - - ...
Page 185
... PERP—Port P Pull Device Enable Register 0x025D PPSP—Port P Polarity Select Register 0x025E PIEP—Port P Interrupt Enable Register 0x025F PIFP—Port P Interrupt Flag Register Freescale Semiconductor Register 4 MC9S12G Family Reference Manual, Rev.1.23 Port Integration Module (S12GPIMV1) Access Reset Value Section/Page ...
Page 186
... R/W 0x00 2.4.3.47/2-237 R/W 0x00 2.4.3.48/2-238 R/W 0x00 2.4.3.49/2-239 R/W 0x00 2.4.3.50/2-239 3 R 2.4.3.51/2-240 3 R 2.4.3.54/2-241 R/W 0x00 2.4.3.53/2-241 R/W 0x00 2.4.3.54/2-241 R(/W) 0x00 (RVA) R/W 0x00 2.4.3.56/2-242 R/W 0x00 2.4.3.57/2-243 R/W 0x00 2.4.3.58/2-244 R/W 0x00 2.4.3.59/2-244 R/W 0x00 2.4.3.60/2-245 R/W 0x00 2.4.3.61/2-246 R/W 0x00 2.4.3.62/2-246 R/W 0x00 2.4.3.63/2-247 R/W 0x00 2.4.3.64/2-248 Rev.1.23 Freescale Semiconductor ...
Page 187
... R PD7 PORTD W 0x0006 R DDRC7 DDRC W 0x0007 R DDRD7 DDRD 0x0008 R 0 PORTE W 0x0009 R 0 DDRE W Freescale Semiconductor NOTE Table 2-19. Block Register Map (G1 PA6 PA5 PA4 PB6 PB5 PB4 DDRA6 DDRA5 DDRA4 DDRB6 DDRB5 DDRB4 PC6 PC5 PC4 PD6 PD5 PD4 ...
Page 188
... PUPCE PUPBE EDIV3 EDIV2 EDIV1 Reserved Reserved Reserved PTT3 PTT2 PTT1 PTIT3 PTIT2 PTIT1 DDRT3 DDRT2 DDRT1 PERT3 PERT2 PERT1 PPST3 PPST2 PPST1 Rev.1.23 Freescale Semiconductor Bit 0 PUPAE 0 EDIV0 0 0 Reserved PTT0 PTIT0 DDRT0 0 PERT0 PPST0 ...
Page 189
... R PRR0P3 PRR0 W 0x0250 R 0 PTM W 0x0251 R 0 PTIM W 0x0252 R 0 DDRM W 0x0253 R 0 Reserved W 0x0254 R 0 PERM W Freescale Semiconductor PTS6 PTS5 PTS4 PTIS6 PTIS5 PTIS4 DDRS6 DDRS5 DDRS4 PERS6 PERS5 PERS4 PPSS6 PPSS5 PPSS4 WOMS6 WOMS5 ...
Page 190
... DDRP1 PERP3 PERP2 PERP1 PPSP3 PPSP2 PPSP1 PIEP3 PIEP2 PIEP1 PIFP3 PIFP2 PIFP1 PTJ3 PTJ2 PTJ1 PTIJ3 PTIJ2 PTIJ1 DDRJ3 DDRJ2 DDRJ1 Rev.1.23 Freescale Semiconductor Bit 0 PPSM0 WOMM0 PKGCR0 PTP0 PTIP0 DDRP0 0 PERP0 PPSP0 PIEP0 PIFP0 0 PTJ0 PTIJ0 DDRJ0 ...
Page 191
... R Reserved W 0x0277 R 0 PRR1 W 0x0278 R PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 PER0AD W 0x0279 R PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 PER1AD W Freescale Semiconductor PERJ6 PERJ5 PERJ4 PPSJ6 PPSJ5 PPSJ4 PIEJ6 PIEJ5 PIEJ4 PIFJ6 PIFJ5 PIFJ4 ...
Page 192
... Unimplemented or Reserved MC9S12G Family Reference Manual PIE0AD3 PIE0AD2 PIE0AD1 PIE1AD3 PIE1AD2 PIE1AD1 PIF0AD3 PIF0AD2 PIF0AD1 PIF1AD3 PIF1AD2 PIF1AD1 PE1 0 0 DDRE1 Rev.1.23 Freescale Semiconductor Bit 0 PIE0AD0 PIE1AD0 PIF0AD0 PIF1AD0 Bit 0 0 PE0 DDRE0 0 0 ...
Page 193
... R PERT7 PERT W 0x0245 R PPST7 PPST W 0x0246 R 0 Reserved W 0x0247 R 0 Reserved W 0x0248 R PTS7 PTS W Freescale Semiconductor Non-PIM Address Range NCLKX2 DIV16 EDIV4 IRQEN Reserved Reserved Reserved Non-PIM Address Range PTT6 PTT5 PTT4 PTIT6 PTIT5 PTIT4 DDRT6 DDRT5 ...
Page 194
... PRR0T21 PRR0T20 PRR0S1 PTM3 PTM2 PTM1 PTIM3 PTIM2 PTIM1 DDRM3 DDRM2 DDRM1 PERM3 PERM2 PERM1 PPSM3 PPSM2 PPSM1 WOMM3 WOMM2 WOMM1 0 PKGCR2 PKGCR1 Rev.1.23 Freescale Semiconductor Bit 0 PTIS0 DDRS0 0 PERS0 PPSS0 WOMS0 PRR0S0 PTM0 PTIM0 DDRM0 0 PERM0 PPSM0 WOMM0 PKGCR0 ...
Page 195
... Reserved W 0x0267 R Reserved Reserved W 0x0268 R PTJ7 PTJ W 0x0269 R PTIJ7 PTIJ W 0x026A R DDRJ7 DDRJ W 0x026B R 0 Reserved W Freescale Semiconductor PTP6 PTP5 PTP4 PTIP6 PTIP5 PTIP4 DDRP6 DDRP5 DDRP4 PERP6 PERP5 PERP4 PPSP6 PPSP5 PPSP4 PIEP6 PIEP5 PIEP4 PIFP6 PIFP5 PIFP4 ...
Page 196
... MC9S12G Family Reference Manual PERJ3 PERJ2 PERJ1 PPSJ3 PPSJ2 PPSJ1 PIEJ3 PIEJ2 PIEJ1 PIFJ3 PIFJ2 PIFJ1 PT0AD3 PT0AD2 PT0AD1 PT1AD3 PT1AD2 PT1AD1 PTI0AD3 PTI0AD2 PTI0AD1 PTI1AD3 PTI1AD2 PTI1AD1 Rev.1.23 Freescale Semiconductor Bit 0 PERJ0 PPSJ0 PIEJ0 PIFJ0 PT0AD0 PT1AD0 PTI0AD0 PTI1AD0 0 0 ...
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... R 0 PORTE W 0x0009 R 0 DDRE W 0x000A–0x000B R Non-PIM W Address Range 0x000C R 0 PUCR W 0x000D R 0 Reserved W Freescale Semiconductor PIE0AD6 PIE0AD5 PIE0AD4 PIE1AD6 PIE1AD5 PIE1AD4 PIF0AD6 PIF0AD5 PIF0AD4 PIF1AD6 PIF1AD5 PIF1AD4 = Unimplemented or Reserved Table 2-21. Block Register Map (G3 ...
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... Reserved Reserved Reserved PTT3 PTT2 PTT1 PTIT3 PTIT2 PTIT1 DDRT3 DDRT2 DDRT1 PERT3 PERT2 PERT1 PPST3 PPST2 PPST1 PTS3 PTS2 PTS1 Rev.1.23 Freescale Semiconductor Bit 0 EDIV0 0 0 Reserved PTT0 PTIT0 DDRT0 0 PERT0 PPST0 0 0 PTS0 ...
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... R 0 DDRM W 0x0253 R 0 Reserved W 0x0254 R 0 PERM W 0x0255 R 0 PPSM W 0x0256 R 0 WOMM W 0x0257 R APICLKS7 PKGCR W Freescale Semiconductor PTIS6 PTIS5 PTIS4 DDRS6 DDRS5 DDRS4 PERS6 PERS5 PERS4 PPSS6 PPSS5 PPSS4 WOMS6 WOMS5 WOMS4 PRR0P2 PRR0T31 PRR0T30 ...
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... PERP3 PERP2 PERP1 PPSP3 PPSP2 PPSP1 PIEP3 PIEP2 PIEP1 PIFP3 PIFP2 PIFP1 PTJ3 PTJ2 PTJ1 PTIJ3 PTIJ2 PTIJ1 DDRJ3 DDRJ2 DDRJ1 PERJ3 PERJ2 PERJ1 Rev.1.23 Freescale Semiconductor Bit 0 PTP0 PTIP0 DDRP0 0 PERP0 PPSP0 PIEP0 PIFP0 0 PTJ0 PTIJ0 DDRJ0 0 PERJ0 ...