S9S12G192F0VLH Freescale Semiconductor, S9S12G192F0VLH Datasheet - Page 774

• Manufacturer Part Number: S9S12G192F0VLH
• Description: 16-bit Microcontrollers - MCU 16BIT 192KB FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G192F0VLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

Timer Module (TIM16B8CV3)
23.4.5
Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7
pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to
increment the count.
The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin
since the last reset.
The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator
overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests.
23.4.6
Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active
level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE
bit selects low levels or high levels to enable the divided-by-64 clock.
The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to
generate interrupt requests.
The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the
last reset.
23.5
The reset state of each individual bit is listed within
which details the registers and their bit fields
23.6
This section describes interrupts originated by the TIM16B8CV3 block.
generated by the TIM16B8CV3 to communicate with the MCU.
776
Resets
Interrupts
Event Counter Mode
Gated Time Accumulation Mode
The PACNT input and timer channel 7 use the same pin IOC7. To use the
IOC7, disconnect it from the output logic by clearing the channel 7 output
mode and output level bits, OM7 and OL7. Also clear the channel 7 output
compare 7 mask bit, OC7M7.
The pulse accumulator counter can operate in event counter mode even
when the timer enable bit, TEN, is clear.
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
MC9S12G Family Reference Manual,
NOTE
NOTE
NOTE
Section 23.3, “Memory Map and Register Definition”
Rev.1.23
Table 23-25
Freescale Semiconductor
lists the interrupts