S9S12G192F0VLH Freescale Semiconductor, S9S12G192F0VLH Datasheet - Page 300

• Manufacturer Part Number: S9S12G192F0VLH
• Description: 16-bit Microcontrollers - MCU 16BIT 192KB FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G192F0VLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

Background Debug Module (S12SBDMV1)
earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
Figure 7-7
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
The receive cases are more complicated.
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
302
Start of Bit Time
(Target MCU)
BDM Clock
Transmit 1
Transmit 0
Perceived
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
Host
Host
Synchronization
Uncertainty
Figure 7-7. BDM Host-to-Target Serial Bit Timing
MC9S12G Family Reference Manual,
Figure 7-8
10 Cycles
shows the host receiving a logic 1 from the target
Target Senses Bit
Rev.1.23
Freescale Semiconductor
Next Bit
Earliest
Start of