S9S12GN48F0VLF Freescale Semiconductor, S9S12GN48F0VLF Datasheet - Page 170

• Manufacturer Part Number: S9S12GN48F0VLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN48F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Port Integration Module (S12GPIMV1)
172
PC7
PC6
PC5
PC4-PC2
PC1-PC0
•
• 100 LQFP: The unbuffered analog output signal DACU1 of the DAC1 module is mapped to this pin if
• Signal priority:
• 100 LQFP: The non-inverting analog input signal AMPP1 of the DAC1 module is mapped to this pin if
• Signal priority:
• 100 LQFP: The inverting analog input signal AMPM1 of the DAC1 module is mapped to this pin if the
• Signal priority:
• 100 LQFP: If routing is active (PRR1[PRR1AN]=1) the ADC analog input channel signals AN15-13 and
• Signal priority:
• 100 LQFP: If routing is active (PRR1[PRR1AN]=1) the ADC analog input channel signals AN11-10 and
• Signal priority:
the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital I/O
function and pull device are disabled.
100 LQFP: DACU1 > GPO
the DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only”
mode. If this pin is used with the DAC then the digital input buffer is disabled.
100 LQFP: GPO
DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only” mode.
If this pin is used with the DAC then the digital input buffer is disabled.
100 LQFP: GPO
their related digital trigger inputs are mapped to these pins. The routed ADC function has no effect on
the output state. Refer to
100 LQFP: GPO
their related digital trigger inputs are mapped to these pins. The routed ADC function has no effect on
the output state. Refer to
100 LQFP: GPO
When routing of ADC channels to PC4-PC0 is selected
(PRR1[PRR1AN]=1) the related bit in the ADC Digital Input Enable
Register (ATDDIEN) must be set to 1 to activate the digital input
function on those pins not used as ADC inputs. If the external trigger
source is one of the ADC channels, the digital input buffer of this
channel is automatically enabled.
MC9S12G Family Reference Manual,
Table 2-8. Port
NOTE/2-171
NOTE/2-171
for input buffer control.
for input buffer control.
C
Pins PC7-0
Rev.1.23
Freescale Semiconductor